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參數(shù)資料
| 型號： | MT80C51T-16R |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | 1 MM HEIGHT, QFP-44 |
| 文件頁數(shù)： | 55/80頁 |
| 文件大小： | 5152K |
| 代理商： | MT80C51T-16R |
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XMEGA A [MANUAL]
8077I–AVR–11/2012
23.
AES and DES Crypto Engines
23.1
Features
Data Encryption Standard (DES) CPU instruction
Advanced Encryption Standard (AES) crypto module
DES Instruction
– Encryption and decryption
– DES supported
– Encryption/decryption in 16 CPU clock cycles per 8-byte block
AES crypto module
– Encryption and decryption
– Supports 128-bit keys
– Supports XOR data load mode to the state memory
– Encryption/decryption in 375 clock cycles per 16-byte block
23.2
Overview
The Advanced Encryption Standard (AES) and Data Encryption Standard (DES) are two commonly used standards for
cryptography. These are supported through an AES peripheral module and a DES CPU instruction, and the
communication interfaces and the CPU can use these for fast, encrypted communication and secure data storage.
DES is supported by an instruction in the AVR CPU. The 8-byte key and 8-byte data blocks must be loaded into the
register file, and then the DES instruction must be executed 16 times to encrypt/decrypt the data block.
The AES crypto module encrypts and decrypts 128-bit data blocks with the use of a 128-bit key. The key and data must
be loaded into the key and state memory in the module before encryption/decryption is started. It takes 375 peripheral
clock cycles before the encryption/decryption is done. The encrypted/encrypted data can then be read out, and an
optional interrupt can be generated. The AES crypto module also has DMA support with transfer triggers when
encryption/decryption is done and optional auto-start of encryption/decryption when the state memory is fully loaded.
23.3
DES Instruction
The DES instruction is a single cycle instruction. In order to decrypt or encrypt a 64-bit (8-byte) data block, the instruction
has to be executed 16 times.
The data and key blocks must be loaded into the register file before encryption/decryption is started. The 64-bit data
block (plaintext or ciphertext) is placed in registers R0-R7, where the LSB of data is placed in R0 and the MSB of data is
placed in R7. The full 64-bit key (including parity bits) is placed in registers R8-R15, with the LSB of the key in R8 and the
MSB of the key in R15.
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