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參數(shù)資料
| 型號(hào)： | MT80C51T-16R |
| 廠商： | ATMEL CORP |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | 1 MM HEIGHT, QFP-44 |
| 文件頁(yè)數(shù)： | 18/80頁(yè) |
| 文件大?。?/td> | 5152K |
| 代理商： | MT80C51T-16R |
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209
2466T–AVR–07/10
ATmega16(L)
Figure 103. ADC Timing Diagram, Auto Triggered Conversion
Figure 104. ADC Timing Diagram, Free Running Conversion
Differential Gain
Channels
When using differential gain channels, certain aspects of the conversion need to be taken into
consideration.
Differential conversions are synchronized to the internal clock CK
ADC2 equal to half the ADC
clock. This synchronization is done automatically by the ADC interface in such a way that the
sample-and-hold occurs at a specific phase of CK
ADC2. A conversion initiated by the user (that is,
Table 81. ADC Conversion Time
Condition
Sample & Hold (Cycles
from Start of
Conversion)
Conversion Time (Cycles)
First conversion
13.5
25
Normal conversions, single ended
1.5
13
Auto Triggered conversions
2
13.5
Normal conversions, differential
1.5/2.5
13/14
1
2
3
4
5
6
7
8
9
10
11
12
13
MSB of Result
LSB of Result
ADC Clock
Trigger
Source
ADIF
ADCH
ADCL
Cycle Number
12
One Conversion
Next Conversion
Conversion
Complete
Prescaler
Reset
ADATE
Prescaler
Reset
Sample & Hold
MUX and REFS
Update
11
12
13
MSB of Result
LSB of Result
ADC Clock
ADSC
ADIF
ADCH
ADCL
Cycle Number
12
One Conversion
Next Conversion
34
Conversion
Complete
Sample & Hold
MUX and REFS
Update
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