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參數(shù)資料
| 型號： | MT6V16M18 |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 512K x 18 x 32 banks RDRAM(512K x 18 x 32組 同步動態(tài)RAM) |
| 中文描述： | 為512k × 18 × 32銀行的RDRAM（為512k × 18 × 32組同步動態(tài)RAM）的 |
| 文件頁數(shù)： | 2/4頁 |
| 文件大?。?/td> | 83K |
| 代理商： | MT6V16M18 |
2
256Mb/288Mb: 16 Meg x 16/18 RDRAM
256MRDRAM_2.p65 – Rev. 7/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
256Mb/288Mb: 16 MEG x 16/18
RDRAM
ADVANCE
GENERAL DESCRIPTION
The MT6V16M16 RDRAM
is a general-purpose,
high-performance, packet-oriented, dynamic random-
access memory containing 268,435,456, bits. The
MT6V16M16 is internally configured as 32 banks of
64K x 128; each of the 64K x 128 banks is organized as
512 rows by 128 columns by 128 bits. The 128 bits are
serially multiplexed onto the RDRAM’s I/O pins as eight
16-bit words.
The MT6V16M18 RDRAM is a general-purpose, high-
performance, packet-oriented, dynamic random-
access memory containing 301,989,888 bits. The
MT6V16M18 is internally configured as 32 banks of
64K x 144; each of the 64K x 144 banks is organized as
512 rows by 128 columns by 144 bits. The 144 bits are
serially multiplexed onto the RDRAM’s I/O pins as eight
18-bit words.
The MT6V16M16/MT6V16M18 use Rambus signal-
ing level (RSL) technology to achieve 300 MHz, 356
MHz or 400 MHz clock speeds using differential clocks.
Control and I/O data is transferred on both rising and
falling edges of the clock. This allows data transfers at
1.25ns per two bytes (10ns per 16 bytes) during peak
operation.
All DRAM commands are communicated to the
MT6V16M16/MT6V16M18 through a 3-bit row or 5-bit
column bus in packets which are 8 bits in length. These
packets are then decoded on the RDRAM into the
operation and address requiring access.
Initialization and mode configuration for the
MT6V16M16/MT6V16M18 are accessed through the
slow-speed CMOS serial I/O interface.
The architecture of RDRAMs allows high sustained
bandwidth memory transactions for multiple, simulta-
neous, semi-random addresses. The RDRAM’s 32 banks
can support up to four simultaneous transactions (within
bank restrictions).
System-oriented features include power manage-
ment, byte masking, and x18 organization. The two
data bits in the x18 organization are general and can be
used for additional storage and bandwidth, or for error
correction. Additionally, the MT6V16M18 includes
interleaved data mode (IDM) which may be used to
enable higher error correction algorithms at system
level.
DEVICE PINOUT
The pinout tables below show the pin assignments
of the center-bonded RDRAM package from the top side
of the package (the view looking down on the package
as it is mounted on the circuit board). The MT6V16M16
and MT6V16M18 devices are available in an FBGA
package with a ball pitch of 0.8mm.
NOTE
: For the MT6V16M16 device, DQA8 and DQB8 are no connects.
FBGA PACKAGE
F2 PINOUT
(TOP VIEW)
10
9
8
7
6
5
4
3
2
1
V
DD
GND
V
DD
GND
V
DD
V
DD
V
DD
V
DD
GND
V
DD
V
DD
DQA8 DQA7 DQA5 DQA3 DQA1 CTMN
CMD
V
DD
GND
GNDa GNDa
V
DD
CTM
V
DD
RQ7
GND
RQ5
GND
RQ3
V
DD
RQ1
V
DD
DQB1 DQB3 DQB5 DQB7 DQB8
GND
GND
V
CMOS
V
DD
GND
GND
DQA6 DQA4 DQA2 DQA0
SCK
V
CMOS
CFM
GND
CFMN
V
DD
a
RQ6
V
REF
RQ4
GND
RQ2
V
DD
RQ0
GND
DQB0 DQB2 DQB4 DQB6
GND
V
DD
GND
GND
GND
V
DD
SIO0
SIO1
V
DD
A
GND
B
GND
D
V
DD
E
GND
F
GND
L
GND
M
GND
N
GND
R
V
DD
S
C
G
H
J
K
P
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