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參數資料
| 型號： | MT5C1008LL |
| 廠商： | Austin Semiconductor, Inc |
| 元件分類： | SRAM |
| 英文描述： | 128K x 8 SRAM WITH DUAL CHIP ENABLE ULTRA LOW POWER |
| 中文描述： | 128K的× 8，配有雙芯片啟用超低功耗的SRAM |
| 文件頁數： | 5/10頁 |
| 文件大?。?/td> | 129K |
| 代理商： | MT5C1008LL |
S R A M
MT5C1008(LL)
Ultra Low Power
Austin Semiconductor, Inc.
MT5C1008(LL)
Rev. 1.0 7/02
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
NOTES:
1. Test conditions assume signal transition time of 3ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified I
OL
/I
OH
and 30pF load capacitance.
2. t
HZOE
, t
HZCE
, and t
HZWE
are specified with a load capacitance of 5pF as in part (b) of AC Test Loads. Transition is measured ±500mV from steady-state voltage.
3. At any given temperature and voltage condition, t
< t
, t
< t
, and t
< t
for any given device.
4. The internal write time of the memory is defined by the overlap of CE1\ LOW, CE2 HIGH, and WE\ LOW. CE1\ and WE\ must be LOW and CE2 HIGH to initiate a write, and the transition of any of
these signals can terminate the write. The input data setup and hold timing should be referenced to the leading edge of the signal that terminates the write.
5. The minimum write cycle time for Write Cycle No. 3 (WE\ controlled, OE\ LOW) is the sum of t
HZWE
and t
SD
.
SWITCHING CHARACTERISTICS
1
(-55
o
C < T
C
< 125
o
C; V
CC
= 5.0V +10%)
PARAMETER
SYM
MIN
MAX
UNITS
NOTES
Read Cycle Time
t
RC
30
ns
Address to Data Valid
t
AA
30
ns
Data Hold from Address Change
t
OHA
3
ns
CE1\ LOW to Data Valid, CE2 HIGH to Data Valid
t
ACE
30
ns
OE\ LOW to Data Valid
t
DOE
12
ns
OE\ LOW to Low Z
t
LZOE
0
ns
OE\ HIGH to High Z
t
HZOE
8
ns
2, 3
CE1\ LOW to Low Z, CE2 HIGH to Low Z
t
LZCE
3
ns
3
CE1\ HIGH to High Z, CE2 LOW to High Z
WRITE CYCLE
4
t
HZCE
15
ns
2, 3
Write Cycle Time
t
WC
30
ns
5
CE1\ LOW to Write End, CE2 HIGH to Write End
t
SCE
22
ns
Address Set-Up to Write End
t
AW
22
ns
Address Hold from Write End
t
HA
0
ns
Address Set-Up to Write Start
t
SA
0
ns
WE\ Pulse Width
t
PWE
22
ns
Data Set-up to Write End
t
SD
18
ns
Data Hold from Write End
t
HD
0
ns
WE\ HIGH to Low Z
t
LZWE
5
ns
3
WE\ LOW to High Z
t
HZWE
8
ns
2, 3
-30
READ CYCLE
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