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參數(shù)資料
| 型號： | MT58L64L32FT-8.5 |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 2Mb: 128K x 18, 64K x 32/36 FLOW-THROUGH SYNCBURST SRAM |
| 中文描述： | 2MB的：128K的× 18，64K的x 32/36流通過SYNCBURST的SRAM |
| 文件頁數(shù)： | 21/24頁 |
| 文件大?。?/td> | 488K |
| 代理商： | MT58L64L32FT-8.5 |
21
2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM
MT58L128L18F_2.p65 – Rev. 8/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
2Mb: 128K x 18, 64K x 32/36
FLOW-THROUGH SYNCBURST SRAM
READ/WRITE TIMING
tKC
tKL
CLK
ADSP#
tADSH
tADSS
ADDRESS
tKH
OE#
ADSC#
CE#
(NOTE 2)
tAH
tAS
A2
tCEH
tCES
BWE#,
BWa#-BWd#
(NOTE 4)
Q
ADV#
Single WRITE
D(A3)
A3
A4
D
BURST READ
Back-to-Back READs
High-Z
Q(A2)
Q(A4)
Q(A4+1)
Q(A4+2)
Q(A4+3)
tWH
tWS
tOEHZ
tDH
tDS
tKQ
tOELZ
(NOTE 1)
A1
A5
A6
D(A5)
D(A6)
Q(A1)
Back-to-Back
WRITEs
DONT CARE
UNDEFINED
NOTE:
1. Q(A4) refers to output from address A4. Q(A4 + 1) refers to output from the next internal burst address following A4.
2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When
CE# is HIGH, CE2# is HIGH and CE2 is LOW.
3. The data bus (Q) remains in High-Z following a WRITE cycle unless an ADSP#, ADSC# or ADV# cycle is performed.
4. GW# is HIGH.
5. Back-to-back READs may be controlled by either ADSP# or ADSC#.
t
WS
t
DS
t
CES
t
AH
t
ADSH
t
WH
t
DH
t
CEH
1.8
1.8
1.8
0.5
0.5
0.5
0.5
0.5
2.0
2.0
2.0
0.5
0.5
0.5
0.5
0.5
2.0
2.0
2.0
0.5
0.5
0.5
0.5
0.5
2.5
2.5
2.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
ns
ns
-6.8
-7.5
-8.5
-10
SYMBOL
MIN MAX MIN MAX MIN MAX MIN MAX
UNITS
READ/WRITE TIMING PARAMETERS
-6.8
-7.5
-8.5
-10
SYMBOL
t
KC
f
KF
t
KH
t
KL
t
KQ
t
OELZ
t
OEHZ
t
AS
t
ADSS
MIN MAX MIN MAX MIN MAX MIN MAX
8.0
8.8
125
113
1.8
1.9
1.8
1.9
6.8
7.5
0
0
3.8
4.2
1.8
2.0
1.8
2.0
UNITS
ns
MHz
ns
ns
ns
ns
ns
ns
ns
10.0
15
100
66
1.9
1.9
4.0
4.0
8.5
10.0
0
0
5.0
5.0
2.0
2.0
2.5
2.5
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT58L64L36FT-10 | 2Mb: 128K x 18, 64K x 32/36 FLOW-THROUGH SYNCBURST SRAM |
| MT58L64L36FT-6.8 | 2Mb: 128K x 18, 64K x 32/36 FLOW-THROUGH SYNCBURST SRAM |
| MT58L64L36FT-7.5 | 2Mb: 128K x 18, 64K x 32/36 FLOW-THROUGH SYNCBURST SRAM |
| MT58L32L32D | 32K x 32,3.3V I/O, Pipelined, DCD SyncBurst SRAM(1Mb,3.3V輸入/輸出，流水線式，雙循環(huán)取消選擇，同步脈沖靜態(tài)存儲器) |
| MT58L32L36D | 32K x 36,3.3V I/O, Pipelined, DCD SyncBurst SRAM(1Mb,3.3V輸入/輸出，流水線式，雙循環(huán)取消選擇，同步脈沖靜態(tài)存儲器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT58L64L32PT-10 | 制造商:Cypress Semiconductor 功能描述: 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Micron Technology Inc 功能描述: |
| MT58L64L32PT-10 TR | 制造商:Cypress Semiconductor 功能描述:64KX32 SRAM PLASTIC TQFP 3.3V |
| MT58L64L32PT-10TR | 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel |
| MT58L64L32PT-6 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Micron Technology Inc 功能描述: |
| MT58L64L32PT-6 TR | 制造商:Cypress Semiconductor 功能描述:64KX32 SRAM PLASTIC TQFP 3.3V |
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