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參數(shù)資料
| 型號： | MT58L32L36D |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 32K x 36,3.3V I/O, Pipelined, DCD SyncBurst SRAM(1Mb,3.3V輸入/輸出，流水線式，雙循環(huán)取消選擇，同步脈沖靜態(tài)存儲器) |
| 中文描述： | 32KX8的36,3.3六/ O的流水線，雙氰胺SyncBurst的SRAM（1兆，3.3V的輸入/輸出，流水線式，雙循環(huán)取消選擇，同步脈沖靜態(tài)存儲器） |
| 文件頁數(shù)： | 10/17頁 |
| 文件大?。?/td> | 326K |
| 代理商： | MT58L32L36D |
1Mb: 64K x 18, 32K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM
MT58L64L18D.p65 – Rev. 9/99
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1999, Micron Technology, Inc.
10
1Mb: 64K x 18, 32K x 32/36
3.3V I/O, PIPELINED, DCD SYNCBURST SRAM
I
DD
OPERATING CONDITIONS AND MAXIMUM LIMITS
(0oC
≤
T
A
≤
+70oC; V
DD
, V
DD
Q = +3.3V +0.3V/-0.165V unless otherwise noted)
DESCRIPTION
Power Supply
Current:
Operating
Power Supply
Current: Idle
CONDITIONS
SYMBOL
TYP
-6
-7.5
-10
UNITS NOTES
Device selected; All inputs
≤
V
IL
or
V
IH
; Cycle time
t
KC MIN;
V
DD
= MAX; Outputs open
Device selected; V
DD
= MAX;
ADSC#, ADSP#, GW#, BWx#, ADV#
V
IH
; All inputs
≤
V
SS
+ 0.2 or
V
DD
- 0.2;
Cycle time
t
KC MIN
Device deselected; V
DD
= MAX;
All inputs
≤
V
SS
+ 0.2 or
V
DD
- 0.2;
All inputs static; CLK frequency = 0
Device deselected; V
DD
= MAX;
All inputs
≤
V
IL
or
V
IH
;
All inputs static; CLK frequency = 0
Device deselected; V
DD
= MAX;
ADSC#, ADSP#, GW#, BWx#, ADV#
V
IH
; All inputs
≤
V
SS
+ 0.2 or
V
DD
- 0.2;
Cycle time
t
KC MIN
I
DD
100
340
280
225
mA
1, 2, 3
I
DD
1
30
85
70
65
mA
1, 2, 3
CMOS Standby
I
SB
2
0.5
10
10
10
mA
2, 3
TTL Standby
I
SB
3
6
25
25
25
mA
2, 3
Clock Running
I
SB
4
30
85
70
65
mA
2, 3
NOTE:
1. I
DD
is specified with no output current and increases with faster cycle times. I
DD
Q increases with faster cycle times and
greater output loading.
2. “ Device deselected” means device is in power-down mode as defined in the truth table. “ Device selected” means
device is active (not in power-down mode).
3. Typical values are measured at 3.3V, 25oC and 10ns cycle time.
4. This parameter is sampled.
CAPACITANCE
DESCRIPTION
Control Input Capacitance
Input/Output Capacitance (DQ)
Address Capacitance
Clock Capacitance
CONDITIONS
T
A
= 25oC; f = 1 MHz;
V
DD
= 3.3V
SYMBOL
C
I
C
O
C
A
C
CK
TYP
2.7
4
2.5
2.5
MAX
3.5
5
3.5
3.5
UNITS
pF
pF
pF
pF
NOTES
4
4
4
4
TQFP THERMAL RESISTANCE
DESCRIPTION
Thermal Resistance
(Junction to Ambient)
CONDITIONS
SYMBOL
θ
JA
TYP
40
UNITS NOTES
oC/W
Test conditions follow standard test methods
and procedures for measuring thermal
impedance, per EIA/JESD51.
4
Thermal Resistance
(Junction to Top of Case)
θ
JC
8
oC/W
4
MAX
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