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參數(shù)資料
| 型號： | MT55L128V32F1T-10 |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 128K X 32 ZBT SRAM, 7.5 ns, PQFP100 |
| 封裝： | PLASTIC, MS-026, TQFP-100 |
| 文件頁數(shù)： | 20/26頁 |
| 文件大?。?/td> | 372K |
| 代理商： | MT55L128V32F1T-10 |
3
4Mb: 256K x 18, 128K x 32/36 Flow-Through ZBT SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L256L18F1_F.p65 – Rev. F, Pub. 1/03 EN
2003, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
FLOW-THROUGH ZBT SRAM
GENERAL DESCRIPTION (continued)
The synchronous inputs include all addresses, all
data inputs, chip enable (CE#), two additional chip
enables for easy depth expansion (CE2, CE2#), cycle
start input (ADV/LD#), synchronous clock enable
(CKE#), byte write enables (BWa#, BWb#, BWc#, and
BWd#) and read/write (R/W#).
Asynchronous inputs include the output enable
(OE#, which may be tied LOW for control signal minimi-
zation), clock (CLK) and snooze enable (ZZ, which may
be tied LOW if unused). There is also a burst mode pin
(MODE) that selects between interleaved and linear
burst modes. MODE may be tied HIGH, LOW or left
unconnected if burst is unused. The flow-through data-
out (Q) is enabled by OE#. WRITE cycles can be from
one to four bytes wide as controlled by the write control
inputs.
All READ, WRITE and DESELECT cycles are initi-
ated by the ADV/LD# input. Subsequent burst ad-
dresses can be internally generated as controlled by
the burst advance pin (ADV/LD#). Use of burst mode
is optional. It is allowable to give an address for each
individual READ and WRITE cycle. BURST cycles wrap
around after the fourth access from a base address.
To allow for continuous, 100 percent use of the data
bus, the flow-through ZBT SRAM uses a LATE WRITE
cycle. For example, if a WRITE cycle begins in clock
cycle one, the address is present on rising edge one.
BYTE WRITEs need to be asserted on the same cycle as
the address. The write data associated with the ad-
dress is required one cycle later, or on the rising edge of
clock cycle two.
Address and write control are registered on-chip to
simplify WRITE cycles. This allows self-timed WRITE
cycles. Individual byte enables allow individual bytes
to be written. During a BYTE WRITE cycle, BWa# con-
trols DQa pins; BWb# controls DQb pins; BWc# controls
DQc pins; and BWd# controls DQd pins. Cycle types
can only be defined when an address is loaded, i.e.,
when ADV/LD# is LOW. Parity/ECC bits are only avail-
able on the x18 and x36 versions.
Micron’s 4Mb ZBT SRAMs operate from a +3.3V VDD
power supply, and all inputs and outputs are LVTTL-
compatible. Users can choose either a 2.5V or 3.3V I/O
version. The device is ideally suited for systems requir-
ing high bandwidth and zero bus turnaround delays.
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| MT55L128V32F1T-11 | 128K X 32 ZBT SRAM, 8.5 ns, PQFP100 |
| MT56C3818LG-35 | 8K X 18 CACHE SRAM, 35 ns, PQFP52 |
| MT58L128V18PF-6 | 128K X 18 STANDARD SRAM, 3.5 ns, PBGA165 |
| MT58L64V36PF-10 | 64K X 36 STANDARD SRAM, 5 ns, PBGA165 |
| MT58L256L36FS-8.8 | 256K X 36 STANDARD SRAM, 7.5 ns, PQFP100 |
相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT55L128V36P1T-10 | 制造商:Cypress Semiconductor 功能描述:128KX36 SRAM PLASTIC TQFP 3.3V 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MT55L128V36P1T10A | 制造商:Micron Technology Inc 功能描述: |
| MT55L128V36P1T-6 | 制造商:Cypress Semiconductor 功能描述:128KX36 SRAM PLASTIC TQFP 3.3V |
| MT55L128V36P1T-7.5 | 制造商:Micron Technology Inc 功能描述: |
| MT55L1MY18PT-10 | 制造商:Cypress Semiconductor 功能描述:1MX18 SRAM PLASTIC TQFP 3.3V P |
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