參數(shù)資料
型號: MT4LC16M4A7DJ-6S
元件分類: DRAM
英文描述: 16M X 4 FAST PAGE DRAM, 60 ns, PDSO32
封裝: 0.400 INCH, PLASTIC, SOJ-32
文件頁數(shù): 17/20頁
文件大?。?/td> 338K
代理商: MT4LC16M4A7DJ-6S
6
16 Meg x 4 FPM DRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D21_2.p65 – Rev. 5/00
2000, Micron Technology, Inc.
16 MEG x 4
FPM DRAM
OBSOLETE
CAPACITANCE
(Note: 2)
PARAMETER
SYMBOL
MAX
UNITS
Input Capacitance: Address pins
CI1
5pF
Input Capacitance: RAS#, CAS#, WE#, OE#
CI2
7pF
Input/Output Capacitance: DQ
CIO
7pF
AC ELECTRICAL CHARACTERISTICS
(Notes: 5, 6, 7, 8, 9, 10, 11, 12) (VCC = +3.3V ±0.3V)
AC CHARACTERISTICS
-5
-6
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
UNITS
NOTES
Access time from column address
tAA
25
30
ns
Column-address hold time (referenced to RAS#)
tAR
40
45
ns
Column-address setup time
tASC
0
ns
Row-address setup time
tASR
0
ns
Column address to WE# delay time
tAWD
48
55
ns
18
Access time from CAS#
tCAC
13
15
ns
Column-address hold time
tCAH
8
10
ns
CAS# pulse width
tCAS
13
10,000
15
10,000
ns
CAS# LOW to “Don’t Care” during Self Refresh
tCHD
15
ns
CAS# hold time (CBR Refresh)
tCHR
15
ns
4
CAS# to output in Low-Z
tCLZ
3
ns
CAS# precharge time (FAST PAGE MODE)
tCP
8
10
ns
13
Access time from CAS# precharge
tCPA
30
35
ns
CAS# to RAS# precharge time
tCRP
5
ns
CAS# hold time
tCSH
50
60
ns
CAS# setup time (CBR Refresh)
tCSR
5
ns
4
CAS# to WE# delay time
tCWD
36
40
ns
18
WRITE command to CAS# lead time
tCWL
13
15
ns
Data-in hold time
tDH
8
10
ns
19
Data-in setup time
tDS
0
ns
19
Output disable
tOD
3
13
3
15
ns
23, 24
Output enable time
tOE
13
15
ns
20
OE# hold time from WE# during
tOEH
13
15
ns
24
READ-MODIFY-WRITE cycle
Output buffer turn-off delay
tOFF
3
13
3
15
ns
17, 23
OE# setup prior to RAS# during
tORD
0
ns
HIDDEN REFRESH cycle
FAST-PAGE-MODE READ or WRITE cycle time
tPC
30
35
ns
FAST-PAGE-MODE READ-WRITE cycle time
tPRWC
76
85
ns
Access time from RAS#
tRAC
50
60
ns
RAS# to column-address delay time
tRAD
13
15
ns
15
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