參數(shù)資料
型號(hào)： MT4C4007J
廠商： Micron Technology, Inc.
英文描述： 1 Meg x 4 EDO DRAM(1M x 4擴(kuò)展數(shù)據(jù)輸出動(dòng)態(tài)RAM)
中文描述： 1梅格× 4 EDO公司的DRAM（3米× 4擴(kuò)展數(shù)據(jù)輸出動(dòng)態(tài)內(nèi)存）
文件頁(yè)數(shù)： 7/16頁(yè)
文件大?。?/td> 204K
代理商： MT4C4007J
1 Meg x 4 EDO DRAM
D23.pm5 – Rev. 3/97
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1997, Micron Technology, Inc.
7
1 MEG x 4
EDO DRAM
OBSOLETE
NOTES
1. All voltages referenced to V
SS
.
2. This parameter is sampled. V
CC
= +4.5V; f = 1 MHz.
3. I
CC
is dependent on output loading and cycle rates.
Specified values are obtained with minimum cycle
time and the outputs open.
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to indicate
cycle time at which proper operation over the full
temperature range is ensured.
6. An initial pause of 100
μ
s is required after power-up,
followed by eight RAS# refresh cycles (RAS#-ONLY
or CBR with WE# HIGH), before proper device
operation is ensured. The eight RAS# cycle wake-ups
should be repeated any time the
t
REF refresh
requirement is exceeded.
7. AC characteristics assume
t
T = 2.5ns.
8. V
IH
(MIN) and V
IL
(MAX) are reference levels for
measuring timing of input signals. Transition times
are measured between V
IH
and V
IL
(or between V
IL
and V
IH
).
9. In addition to meeting the transition rate specifica-
tion, all input signals must transit between V
IH
and
V
IL
(or between V
IL
and V
IH
) in a monotonic manner.
10. If CAS# and RAS# = V
IH
, data output is High-Z.
11. If CAS# = V
IL
, data output may contain data from the
last valid READ cycle.
12. Measured with a load equivalent to two TTL gates
and 100pF.
13. If CAS# is LOW at the falling edge of RAS#, Q will be
maintained from the previous cycle. To initiate a new
cycle and clear the data-out buffer, CAS# must be
pulsed HIGH for
t
CP.
14. The
t
RAD (MAX) limit is no longer specified.
t
RAD
(MAX) was specified as a reference point only. If
t
RAD was greater than the specified
t
RAD (MAX)
limit, then access time was controlled exclusively by
t
AA (
t
RAC and
t
CAC no longer applied). With or
without the
t
RAD (MAX) limit,
t
AA,
t
RAC and
t
CAC
must always be met.
15. The
t
RCD (MAX) limit is no longer specified.
t
RCD
(MAX) was specified as a reference point only. If
t
RCD was greater than the specified
t
RCD (MAX)
limit, then access time was controlled exclusively by
t
CAC (
t
RAC [MIN] no longer applied). With or
without the
t
RCD limit,
t
AA and
t
CAC must always
be met.
16. Either
t
RCH or
t
RRH must be satisfied for a READ
cycle.
17.
t
OFF (MAX) defines the time at which the output
achieves the open circuit condition and is not
referenced to V
OH
or V
OL
.
18. If OE# is tied permanently LOW, LATE WRITE or
READ-MODIFY-WRITE operations are not possible.
19. These parameters are referenced to CAS# leading
edge in EARLY WRITE cycles.
20. Even if OE# is HIGH, LATE WRITE or READ-
MODIFY-WRITE operations are not permissible and
should not be attempted.
21. A HIDDEN REFRESH may also be performed after a
WRITE cycle. In this case, WE# is LOW and OE# is
HIGH.
22. The DQs open during READ cycles once
t
OD or
t
OFF
occur.
23. Extended refresh current is reduced as
t
RAS is
reduced from its maximum specification during the
extended refresh cycle.
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