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參數(shù)資料
| 型號： | MT49H16M18CFM-xx |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 288Mb SIO REDUCED LATENCY(RLDRAM II) |
| 中文描述： | 288Mb二氧化硅約化延遲（延遲DRAM二） |
| 文件頁數(shù)： | 16/44頁 |
| 文件大?。?/td> | 1117K |
| 代理商： | MT49H16M18CFM-XX |
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16 MEG x 18, 32 MEG x 9
2.5V V
EXT
, 1.8V V
DD
, HSTL, SIO, RLDRAM II
pdf: 09005aef80a41b59/zip: 09005aef811ba111
MT49H8M18C_2.fm - Rev. F 11/04 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2004 Micron Technology, Inc. All rights reserved.
16
Mode Register Set Command (MRS)
The mode register stores the data for controlling the
operating modes of the memory. It programs the
RLDRAM configuration, burst length, test mode, and
I/O options. During a MRS command, the address
inputs A(17:0) are sampled and stored in the mode reg-
ister.
t
MRSC must be met before any command can be
issued to the RLDRAM. The mode register may be set
at any time during device operation. However, any
pending operations are not guaranteed to successfully
complete. See the RLDRAM II design guide for more
details.
Figure 8: Mode Register Set Timing
NOTE:
MRS: MRS command and AC: any command.
Figure 9: Mode Register Set
NOTE:
COD: code to be loaded into the register.
Figure 10: Mode Register Bit Map
NOTE:
1. Bits A(17:10)
must
be set to zero.
2. BL = 8 is not available for configuration 1.
3. ±15% temperature variation.
CK#
CK
CMD
t
MRSC
MRS
NOP
NOP
AC
DON’T CARE
CK#
CK
WE#
REF#
A(17:0)
CS#
COD
A(20:18)
BA(2:0)
DON’T CARE
A2
A4
A5
A(17:10)
A3
A1
A0
A6
A7
A3
0
1
BL
4
8
2
A4
0
1
0
0
1
1
Reserved
1
A9
A7
0
1
A8
A2
A1
A0
1
1
0
1
Configuration
Configuration
CoRLDRAM
1
2
(default)
1
2
2
reserved
reserved
reserved
not valid
2 (default)
DLL enabled
DLL Reset
DLL Reset
Burst Length
Burst Length
DLL Reset
Address
Mux
Address Mux
DLL reset (default)
3
reserved
1
1
0
1
0
1
0
0
1
0
0
0
1
1
0
0
1
0
1
0
Impedance
Matching
Impedance
Matching
A8
0
1
Resistor
external
internal 50
3
(default)
A5
0
1
nonmultiplexed
(default)
address multiplexed
Address Mux
A9
0
1
Enabled
Termination
On-Die
Termination
Disabled (default)
On-Die
Termination
Unused
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|---|---|
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