參數(shù)資料
型號： MT49H16M18CFM-xx
廠商： Micron Technology, Inc.
英文描述： 288Mb SIO REDUCED LATENCY(RLDRAM II)
中文描述： 288Mb二氧化硅約化延遲（延遲DRAM二）
文件頁數(shù)： 12/44頁
文件大?。?/td> 1117K
代理商： MT49H16M18CFM-XX
16 MEG x 18, 32 MEG x 9
2.5V V
EXT
, 1.8V V
DD
, HSTL, SIO, RLDRAM II
pdf: 09005aef80a41b59/zip: 09005aef811ba111
MT49H8M18C_2.fm - Rev. F 11/04 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2004 Micron Technology, Inc. All rights reserved.
12
NOTE:
1. All timing parameters are measured relative to the crossing point of CK/CK#, DK/DK# and to the crossing point with V
REF
of the command, address, and data signals.
2. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
3.
t
QKQ0 is referenced to Q0–Q8 in x18.
t
QKQ1 is referenced to Q9–Q17 in x18.
4.
t
QKQ takes into account the skew between any QKx and any Q.
Table 6:
Note 1
AC Electrical Characteristics
DESCRIPTION
SYMBOL
-25
-33
-5
UNITS
NOTES
MIN
MAX
MIN
MAX
MIN
MAX
Clock
Clock cycle time
t
CK,
t
DK
f
CK,
f
DK
t
CK
VAR
t
CKH,
t
DKH
t
CKL,
t
DKL
t
CKDK
t
MRSC
2.5
5.7
3.3
5.7
5.0
5.7
ns
System frequency
175
400
175
300
175
200
MHz
Clock phase jitter
0.15
0.20
0.25
ns
2
Clock HIGH time
0.45
0.55
0.45
0.55
0.45
0.55
t
CK
t
CK
ns
Clock LOW time
0.45
0.55
0.45
0.55
0.45
0.55
Clock to input data clock
-0.3
0.5
-0.3
1.0
-0.3
1.5
Mode register set cycle time to
any command
Setup Times
Address/command and input
setup time
Data-in and data mask to DK
setup time
Hold Times
Address/command and input
hold time
Data-in and data mask to DK
hold time
Data and Data Strobe
Output data clock HIGH time
6
6
6
t
CK
t
AS/
t
CS
0.4
0.5
0.8
ns
t
DS
0.25
0.3
0.4
ns
t
AH/
t
CH
0.4
0.5
0.8
ns
t
DH
0.25
0.3
0.4
ns
t
QKH
t
QKL
t
CKQK
t
QKQ0,
t
QKQ1
t
QKQ
0.9
1.1
0.9
1.1
0.9
1.1
t
CKH
t
CKL
ns
Output data clock LOW time
0.9
1.1
0.9
1.1
0.9
1.1
QK edge to clock edge skew
-0.25
0.25
-0.3
0.3
-0.5
0.5
QK edge to output data edge
-0.2
0.2
-0.25
0.25
-0.3
0.3
ns
3
QK edge to any output data
edge
QK edge to QVLD
-0.3
0.3
-0.35
0.35
-0.4
0.4
ns
4
t
QKVLD
-0.3
0.3
-0.35
0.35
-0.4
0.4
ns
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