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參數(shù)資料
| 型號(hào)： | MT48LC8M16A2 |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | SYNCHRONOUS DRAM |
| 中文描述： | 同步DRAM |
| 文件頁(yè)數(shù)： | 3/4頁(yè) |
| 文件大小： | 115K |
| 代理商： | MT48LC8M16A2 |
128Mb x16
SDRAM Addendum
PRELIMINARY
x16 Addendum
MT48lc8m16a2_addendum.fm - Rev 7/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
3
2002, Micron Technology Inc.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
Notes 5, 6, 8, 9,11; Notes appear on in the standard data sheet
AC CHARACTERISTICS
-6A
PARAMETER
SYMBOL
MIN
MAX
UNITS
NOTES
Access time from CLK (pos. edge)
CL = 3
t
AC(3)
t
AH
t
AS
t
CH
t
CL
t
CK(3)
t
CKH
t
CKS
t
CMH
t
CMS
t
DH
t
DS
t
HZ(3)
t
LZ
t
OH
5.4
ns
27
Address hold time
0.8
ns
Address setup time
1.5
ns
CLK high-level width
2.5
ns
CLK low-level width
2.5
ns
Clock cycle time
CL = 3
6
ns
23
CKE hold time
0.8
ns
CKE setup time
1.5
ns
CS#, RAS#, CAS#, WE#, DQM hold time
0.8
ns
CS#, RAS#, CAS#, WE#, DQM setup time
1.5
ns
Data-in hold time
0.8
ns
Data-in setup time
1.5
ns
Data-out high-impedance time
CL = 3
5.4
ns
10
Data-out low-impedance time
1
ns
Data-out hold time (load)
3
ns
Data-out hold time (no load)
t
OH
N
t
RAS
t
RC
t
RCD
t
REF
t
RFC
t
RP
t
RRD
t
T
t
WR
1.8
ns
28
ACTIVE to PRECHARGE command
42
120,000
ns
ACTIVE to ACTIVE command period
60
ns
ACTIVE to READ or WRITE delay
18
ns
Refresh period (4,096 rows)
64
ms
AUTO REFRESH period
60
ns
PRECHARGE command period
18
ns
ACTIVE bank a to ACTIVE bank b command
12
ns
7
Transition time
0.3
1.2
ns
WRITE recovery time
1
1 CLK +
6ns
12
67
ns
ns
ns
25
20
Exit SELF REFRESH to ACTIVE command
t
XSR
NOTE:
1. Auto precharge mode only. The precharge timing budget (
t
RP) begins 6ns for -6A after the first clock delay, after the last WRITE is
executed. May not exceed limit set for precharge mode.
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| MT48LC8M16A2-75B | 制造商:Micron Technology Inc 功能描述: |
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