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參數(shù)資料
| 型號： | MT48LC4M32TG-10 |
| 元件分類： | DRAM |
| 英文描述： | 4M X 32 SYNCHRONOUS DRAM, 7 ns, PDSO54 |
| 封裝： | 0.400 INCH, PLASTIC, TSOP2-54 |
| 文件頁數(shù)： | 27/69頁 |
| 文件大?。?/td> | 6213K |
| 代理商： | MT48LC4M32TG-10 |
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128Mb: x16, x32
MOBILE SDRAM
09005aef8071a76b
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mbx16x32Mobile_2.fm - Rev. G (DRAFT) 7/04 EN
33
2001 Micron Technology, Inc. All rights reserved.
CONCURRENT Auto Precharge
An access command (READ or WRITE) to another
bank while an access command with auto precharge
enabled is executing is not allowed by SDRAMs, unless
the SDRAM supports Concurrent Auto precharge.
Micron SDRAMs support Concurrent Auto precharge.
Four cases where Concurrent Auto precharge occurs
are defined below.
READ with Auto Precharge
1. Interrupted by a READ (with or without auto pre-
charge): A READ to bank m will interrupt a READ on
bank n, CAS latency later. The precharge to bank n
will begin when the READ to bank m is registered
2. Interrupted by a WRITE (with or without auto pre-
charge): A WRITE to bank m will interrupt a READ
on bank n when registered. DQM should be used
two clocks prior to the WRITE command to prevent
bus contention. The precharge to bank n will begin
when the WRITE to bank m is registered (Figure 32).
Figure 31: READ With Auto Precharge Interrupted by a READ
DON’T CARE
CLK
DQ
DOUT
a
T2
T1
T4
T3
T6
T5
T0
COMMAND
READ - AP
BANK n
NOP
DOUT
a + 1
DOUT
d
DOUT
d + 1
NOP
T7
BANK n
CAS Latency = 3 (BANK m)
BANK m
ADDRESS
Idle
NOP
NOTES:
1) DQM is LOW.
2) Burst length = 4 or greater
3) CAS Latency = 3.
BANK n,
COL a
BANK m,
COL d
READ - AP
BANK m
Internal
States
t
Page Active
READ with Burst of 4
Interrupt Burst, Precharge
Page Active
READ with Burst of 4
Precharge
RP - BANK n
tRP - BANK m
CAS Latency = 3 (BANK n)
TRANSITIONING DATA
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