參數(shù)資料
型號(hào)： MT48LC32M8A2
廠商： Micron Technology, Inc.
英文描述： SYNCHRONOUS DRAM
中文描述： 同步DRAM
文件頁(yè)數(shù)： 4/62頁(yè)
文件大?。?/td> 1517K
代理商： MT48LC32M8A2
4
256Mb: x4, x8, x16 SDRAM
256MSDRAM_E.p65
–
Rev. E; Pub. 3/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2002, Micron Technology, Inc.
256Mb: x4, x8, x16
SDRAM
GENERAL DESCRIPTION
The 256Mb SDRAM is a high-speed CMOS,
dynamic
random-access
268,435,456 bits. It is internally configured as a quad-
bank DRAM with a synchronous interface (all signals
are registered on the positive edge of the clock signal,
CLK). Each of the x4’s 67,108,864-bit banks is orga-
nized as 8,192 rows by 2,048 columns by
4 bits. Each of the x8’s 67,108,864-bit banks is orga-
nized as 8,192 rows by 1,024 columns by 8 bits. Each of
the x16’s 67,108,864-bit banks is organized as 8,192
rows by 512 columns by 16 bits.
Read and write accesses to the SDRAM are burst
oriented; accesses start at a selected location and con-
tinue for a programmed number of locations in a pro-
grammed sequence. Accesses begin with the registra-
tion of an ACTIVE command, which is then followed by
a READ or WRITE command. The address bits regis-
tered coincident with the ACTIVE command are used
memory
containing
PART NUMBER ARCHITECTURE PACKAGE
MT48LC64M4A2TG
64 Meg x 4
MT48LC64M4A2FB*
64 Meg x 4
MT48LC32M8A2TG
32 Meg x 8 54-pin TSOP II
MT48LC32M8A2FB*
32 Meg x 8 60-ball FBGA
MT48LC16M16A2TG
16 Meg x 16 54-pin TSOP II
MT48LC16M16A2FG
16 Meg x 16 54-ball FBGA
*Actual FBGA part marking shown on page 58.
54-pin TSOP II
60-ball FBGA
256 Mb SDRAM PART NUMBERS
to select the bank and row to be accessed (BA0, BA1
select the bank; A0–A12 select the row). The address
bits registered coincident with the READ or WRITE com-
mand are used to select the starting column location
for the burst access.
The SDRAM provides for programmable READ or
WRITE burst lengths of 1, 2, 4, or 8 locations, or the full
page, with a burst terminate option. An auto precharge
function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst se-
quence.
The 256Mb SDRAM uses an internal pipelined ar-
chitecture to achieve high-speed operation. This ar-
chitecture is compatible with the 2
n
rule of prefetch
architectures, but it also allows the column address to
be changed on every clock cycle to achieve a high-
speed, fully random access. Precharging one bank
while accessing one of the other three banks will hide
the precharge cycles and provide seamless, high-
speed, random-access operation.
The 256Mb SDRAM is designed to operate in 3.3V
memory systems. An auto refresh mode is provided,
along with a power-saving, power-down mode. All in-
puts and outputs are LVTTL-compatible.
SDRAMs offer substantial advances in DRAM oper-
ating performance, including the ability to synchro-
nously burst data at a high data rate with automatic
column-address generation, the ability to interleave
between internal banks to hide precharge time and
the capability to randomly change column addresses
on each clock cycle during a burst access.
相關(guān)PDF資料
PDF描述
MT48LC16M16A2 SYNCHRONOUS DRAM
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MT48LC64M8A2 SYNCHRONOUS DRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT48LC32M8A2-75 制造商:Micron Technology Inc 功能描述:
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