參數(shù)資料
型號(hào)： MT48LC32M16A2
廠商： Micron Technology, Inc.
英文描述： SYNCHRONOUS DRAM
中文描述： 同步DRAM
文件頁(yè)數(shù)： 16/55頁(yè)
文件大小： 1828K
代理商： MT48LC32M16A2
16
512Mb: x4, x8, x16 SDRAM
512MSDRAM_D.p65
–
Rev. D; Pub 1/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
512Mb: x4, x8, x16
SDRAM
ADVANCE
latencies of two and three; data element
n
+ 3 is either the
last of a burst of four or the last desired of a longer burst.
The 512Mb SDRAM uses a pipelined architecture and
therefore does not require the 2
n
rule associated with a
prefetch architecture. A READ command can be initiated
Figure 7
Consecutive READ Bursts
on any clock cycle following a previous READ command.
Full-speed random read accesses can be performed to
the same bank, as shown in Figure 8, or each subsequent
READ may be performed to a different bank.
DON
’
T CARE
NOTE:
Each READ command may be to any bank. DQM is LOW.
CLK
DQ
D
OUT
n
T2
T1
T4
T3
T6
T5
T0
COMMAND
ADDRESS
READ
NOP
NOP
NOP
NOP
BANK,
COL
n
NOP
BANK,
COL
b
D
OUT
n
+ 1
D
OUT
n
+ 2
D
OUT
n
+ 3
D
OUT
b
READ
X = 1 cycle
CAS Latency = 2
CLK
DQ
D
OUT
n
T2
T1
T4
T3
T6
T5
T0
COMMAND
ADDRESS
READ
NOP
NOP
NOP
NOP
BANK,
COL
n
NOP
BANK,
COL
b
D
OUT
n
+ 1
D
OUT
n
+ 2
D
OUT
n
+ 3
D
OUT
b
READ
NOP
T7
X = 2 cycles
CAS Latency = 3
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參數(shù)描述
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