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參數(shù)資料
| 型號(hào)： | MT46V64M4 |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 16 Meg x 4 x 4 banks DDR SDRAM(16M x 4 x 4組,雙數(shù)據(jù)速率同步動(dòng)態(tài)RAM) |
| 中文描述： | 16梅格× 4 × 4銀行DDR SDRAM內(nèi)存（1,600 × 4 × 4組，雙數(shù)據(jù)速率同步動(dòng)態(tài)RAM）的 |
| 文件頁數(shù)： | 15/69頁 |
| 文件大?。?/td> | 2410K |
| 代理商： | MT46V64M4 |
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15
256Mb: x4, x8, x16 DDR SDRAM
256Mx4x8x16DDR_B.p65
–
Rev. B; Pub. 7/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
256Mb: x4, x8, x16
DDR SDRAM
ADVANCE
AUTO REFRESH
AUTO REFRESH is used during normal operation
of the DDR SDRAM and is analogous to CAS#-BE-
FORE-RAS# (CBR) REFRESH in FPM/EDO DRAMs.
This command is nonpersistent, so it must be issued
each time a refresh is required.
The addressing is generated by the internal refresh
controller. This makes the address bits a “Don’t Care”
during an AUTO REFRESH command. The 256Mb DDR
SDRAM requires AUTO REFRESH cycles at an average
interval of 7.8125μs (maximum).
To allow for improved efficiency in scheduling and
switching between tasks, some flexibility in the absolute
refresh interval is provided. A maximum of eight AUTO
REFRESH command can be posted to any given DDR
SDRAM, meaning that the maximum absolute interval
between any AUTO REFRESH command and the next
AUTO REFRESH command is 9 × 7.8125μs (70.3μs). This
maximum absolute interval is to allow future support for
DLL updates internal to the DDR SDRAM to be restricted
to AUTO REFRESH cycles, without allowing excessive
drift in
t
AC between updates.
Although not a JEDEC requirement, to provide for
future functionality features, CKE must be active (High)
during the AUTO REFRESH period. The AUTO RE-
FRESH period begins when the AUTO REFRESH com-
mand is registered and ends
t
RFC latter.
SELF REFRESH
The SELF REFRESH command can be used to retain
data in the DDR SDRAM, even if the rest of the system is
powered down. When in the self refresh mode, the DDR
SDRAM retains data without external clocking. The
SELF REFRESH command is initiated like an AUTO
REFRESH command except CKE is disabled (LOW). The
DLL is automatically disabled upon entering SELF RE-
FRESH and is automatically enabled upon exiting SELF
REFRESH (200 clock cycles must then occur before a
READ command can be issued). Input signals except
CKE are “Don’t Care” during SELF REFRESH.
The procedure for exiting self refresh requires a se-
quence of commands. First, CK must be stable prior to
CKE going back HIGH. Once CKE is HIGH, the DDR
SDRAM must have NOP commands issued for
t
XSNR
because time is required for the completion of any
internal refresh in progress. A simple algorithm for
meeting both refresh and DLL requirements is to apply
NOPs for 200 clock cycles before applying any other
command.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT46V64M4_1 | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:Double Data Rate (DDR) SDRAM |
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