![](http://datasheet.mmic.net.cn/390000/MT46V4M32_datasheet_16823570/MT46V4M32_58.png)
58
128Mb: x32 DDR SDRAM
4M32DDR_B.p65 – Rev. B, Pub. 7/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2002, Micron Technology, Inc.
128Mb: x32
DDR SDRAM
ADVANCE
AUTO REFRESH MODE
CK
CK#
COMMAND
1
NOP
2
VALID
VALID
NOP
2
NOP
2
PRE
CKE
RA
A0-A7, A9-A11
A8
1
BA0, BA1
1
Bank(s)
3
BA
NOTE
:
1. PRE = PRECHARGE, ACT = ACTIVE, AR = AUTO REFRESH, RA = Row Address, BA = Bank Address.
2. NOP commands are shown for ease of illustration; other valid commands may be possible at these times.
3. Don t Care if A8 is HIGH at this point; A8 must be HIGH if more than one bank is active (i.e., must precharge all active banks).
4. DM, DQ and DQS signals are all Don t Care /High-Z for operations shown.
5. The second AUTO REFRESH is not required and is only shown as an example of two back-to-back AUTO REFRESH commands.
AR
NOP
2
AR
5
NOP2
ACT
NOP2
ONE BANK
ALL BANKS
t
CK
t
CH
t
CL
t
IS
t
IS
t
IH
t
IH
t
IS
t
IH
RA
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
DQ
4
DM
4
DQS
4
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
(
)
(
)
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
(
)
(
)
)
(
)
(
)
tRFC
5
tRP
tRFC
T0
T1
T2
T3
T4
Ta0
Tb0
Ta1
Tb1
Tb2
DON T CARE
TIMING PARAMETERS
-33
-4
-5
SYMBOL
t
CH
t
CL
t
CK (5)
t
CK (4)
MIN
0.45
0.45
3.3
4
MAX
0.55
0.55
8
8
MIN
0.45
0.45
-
4
MAX
0.55
0.55
-
8
MIN
0.45
0.45
-
-
MAX
0.55
0.55
-
-
UNITS
t
CK
t
CK
ns
ns
-33
-4
-5
SYMBOL
t
CK (3)
t
IH
t
IS
t
RFC
t
RP
MIN
-
0.9
0.9
62
16
MAX
-
MIN
-
0.9
0.9
62
16
MAX
-
MIN
5
0.9
0.9
62
20
MAX
8
UNITS
ns
ns
ns
ns
ns