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參數(shù)資料
| 型號： | MT46V32M81AZ4-6T:G |
| 元件分類： | DRAM |
| 英文描述： | 32M X 4 DDR DRAM, 0.75 ns, PDSO66 |
| 封裝： | 0.400 INCH, PLASTIC, TSOP-66 |
| 文件頁數(shù)： | 5/82頁 |
| 文件大?。?/td> | 2866K |
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128Mb: x4, x8, x16
DDR SDRAM
09005aef8074a655
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128MBDDRx4x8x16_2.fm - Rev. J 7/04 EN
13
2000 Micron Technology, Inc. All rights reserved.
Burst Length
Read and write accesses to the DDR SDRAM are
burst oriented, with the burst length being program-
mable, as shown in Figure 7. The burst length deter-
mines the maximum number of column locations that
can be accessed for a given READ or WRITE command.
Burst lengths of 2, 4, or 8 locations are available for
both the sequential and the interleaved burst types.
Reserved states should not be used, as unknown
operation or incompatibility with future versions may
result.
When a READ or WRITE command is issued, a block
of columns equal to the burst length is effectively
selected. All accesses for that burst take place within
this block, meaning that the burst will wrap within the
block if a boundary is reached. The block is uniquely
selected by A1-Ai when the burst length is set to two,
by A2-Ai when the burst length is set to four and by A3-
Ai when the burst length is set to eight (where Ai is the
most significant column address bit for a given config-
uration). The remaining (least significant) address
bit(s) is (are) used to select the starting location within
the block. The programmed burst length applies to
both READ and WRITE bursts.
Burst Type
Accesses within a given burst may be programmed
to be either sequential or interleaved; this is referred to
as the burst type and is selected via bit M3.
The ordering of accesses within a burst is deter-
mined by the burst length, the burst type and the start-
ing column address, as shown in Table 4, Burst
Figure 7: Mode Register Definition
Operating Mode
Normal Operation
Normal Operation/Reset DLL
All other states reserved
0
1
-
0
-
0
-
0
-
0
-
Valid
-
0
1
Burst Type
Sequential
Interleaved
CAS Latency
Reserved
2
Reserved
2.5
Reserved
Burst Length
CAS Latency BT
0*
A9
A7 A6 A5 A4 A3
A8
A2 A1 A0
Mode Register (Mx)
Address Bus
9
7
65
4
3
8
2
1
0
M3
M4
0
1
0
1
0
1
0
1
M5
0
1
0
1
M6
0
1
M6-M0
M8 M7
Operating Mode
A10
A11
BA0
BA1
10
11
12
0*
13
* M13 and M12 (BA1 and BA0)
must be “0, 0” to select the
base mode register (vs. the
extended mode register).
M9
M10
M11
Burst Length
Reserved
2
4
8
Reserved
M0
0
1
0
1
0
1
0
1
M1
0
1
0
1
M2
0
1
DDR400
CAS Latency
Reserved
2
3
Reserved
2.5
Reserved
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相關代理商/技術參數(shù) |
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