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參數(shù)資料
| 型號： | MT46V2M32V1 |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | DOUBLE DATA RATE DDR SDRAM |
| 中文描述： | 雙倍數(shù)據(jù)速率的DDR SDRAM內(nèi)存 |
| 文件頁數(shù)： | 9/65頁 |
| 文件大?。?/td> | 2360K |
| 代理商： | MT46V2M32V1 |
9
64Mb: x32 DDR SDRAM
2M32DDR-07.p65
–
Rev. 12/01
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2001, Micron Technology, Inc.
64Mb: x32
DDR SDRAM
Table 2
CAS Latency
Operating Mode
The normal operating mode is selected by issuing a
MODE REGISTER SET command with bits A7-A10 each
set to zero, and bits A0-A6 set to the desired values. A
DLL reset is initiated by issuing a MODE REGISTER
SET command with bits A7, A9 - A10 each set to zero, bit
A8 set to one, and bits A0-A6 set to the desired values.
Although not required by the Micron device, JEDEC
specifications recommend when a LOAD MODE REG-
ISTER command is issued to reset the DLL, it should
always be followed by a LOAD MODE REGISTER com-
mand to select normal operating mode.
All other combinations of values for A7-A10 are re-
served for future use and/or test modes. Test modes
and reserved states should not be used because un-
known operation or incompatibility with future ver-
sions may result.
Figure 2
CAS Latency
CK
CK#
COMMAND
DQ
DQS
CL = 2
READ
NOP
NOP
NOP
READ
NOP
NOP
NOP
Burst Length = 4 in the cases shown
Shown with nominal tAC and nominal tDSDQ
CK
CK#
COMMAND
DQ
DQS
CL = 3
T0
T1
T2
T2n
T3
T3n
T0
T1
T2
T3
T3n
DON
’
T CARE
TRANSITIONING DATA
ALLOWABLE OPERATING
FREQUENCY (MHz)
CL = 2
83
≤
f
≤
125
83
≤
f
≤
100
83
≤
f
≤
100
83
≤
f
≤
100
SPEED
-5
-55
-6
-65
CL = 3
83
≤
f
≤
200
83
≤
f
≤
183
83
≤
f
≤
166
83
≤
f
≤
150
Burst Type
Accesses within a given burst may be programmed
to be either sequential or interleaved; this is referred to
as the burst type and is selected via bit M3.
The ordering of accesses within a burst is deter-
mined by the burst length, the burst type and the start-
ing column address, as shown in Table 1.
Read Latency
The READ latency is the delay, in clock cycles, be-
tween the registration of a READ command and the
availability of the first bit of output data. The latency
can be set to 2 or 3 clocks, as shown in Figure 2.
If a READ command is registered at clock edge
n
,
and the latency is
m
clocks, the data will be available
nominally coincident with clock edge
n + m
. Table 2
indicates the operating frequencies at which each CAS
latency setting can be used.
Reserved states should not be used as unknown
operation or incompatibility with future versions may
result.
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