參數(shù)資料
型號: MT36JBZS51272PIY-1G3XX
元件分類: DRAM
英文描述: DDR DRAM MODULE, DMA240
封裝: LEAD FREE, RDIMM-240
文件頁數(shù): 6/21頁
文件大小: 623K
代理商: MT36JBZS51272PIY-1G3XX
PDF: 09005aef8328da34/Source: 09005aef8328daed
Micron Technology, Inc., reserves the right to change products or specifications without notice.
JBZS36C512x72PY.fm - Rev. C 12/08 EN
14
2008 Micron Technology, Inc. All rights reserved.
4GB (x72, ECC, DR): 240-Pin DDR3 SDRAM VLP RDIMM
Temperature Sensor with Serial Presence-Detect EEPROM
The compare mode is similar to the interrupt mode, except EVENT# cannot be reset by
the user and only returns to the logic HIGH state when the temperature falls below the
programmed thresholds.
Critical temperature mode triggers EVENT# only when the temperature has exceeded
the programmed critical trip point. When the critical trip point has been reached, the
temperature sensor goes into comparator mode, and the critical EVENT# cannot be
cleared through software.
SM Bus Slave Subaddress Decoding
The temperature sensor’s physical address differs from the SPD EEPROM’s physical
address: 0011 for A0, A1, A2, and RW# in binary where A2, A1, and A0 are the three slave
subaddress pins and the RW# bit is the READ/WRITE flag.
If the slave base address is fixed for the temperature sensor/SPD EEPROM, then the pins
set the subaddress bits of the slave address, enabling the devices to be located anywhere
within the eight slave address locations. For example, they could be set from 30h to 3Eh.
Figure 3:
EVENT# Pin Functionality
Time
Temperature
Critical
Alarm window (MAX)
Alarm window (MIN)
EVENT#
interrupt mode
EVENT#
comparator mode
EVENT#
critical temperature only mode
Clears event
Hysteresis affects
these trip points
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