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參數(shù)資料
| 型號： | MT18HTF12872G-40EC2 |
| 元件分類： | DRAM |
| 英文描述： | 128M X 72 DDR DRAM MODULE, 0.6 ns, DMA240 |
| 封裝： | DIMM-240 |
| 文件頁數(shù)： | 11/36頁 |
| 文件大?。?/td> | 672K |
| 代理商： | MT18HTF12872G-40EC2 |
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512MB, 1GB, 2GB (x72, REGISTERED)
PC2-3200, PC2-4300, 240-Pin DDR2 SDRAM DIMM
09005aef80e5e626
Micron Technology, Inc., reserves the right to change products or specifications without notice.
HTF18C64_128_256x72G_A.fm - Rev. A 9/03 EN
19
2003 Micron Technology. Inc.
Idd Specifications and Conditions
IDD specifications are tested after the device is prop-
erly initialized. 0°C
TOPR +55°C. VDD = +1.8V ±0.1V,
VDDQ = +1.8V ±0.1V, VDDL = +1.8V ±0.1V, VREF = VDDQ/
2.
Input slew rate is specified by AC Parametric Test
Conditions. IDD parameters are specified with ODT
disabled. Data bus consists of DQ, DQS, and DQS#. IDD
values must be met with all combinations of EMR bits
10 and 11.
Definitions for IDD Conditions:
LOW is defined as VIN
VIL (AC) (MAX)
HIGH is defined as VIN
VIH (AC) (MIN)
STABLE is defined as inputs stable at a HIGH or
LOW level
FLOATING is defined as inputs at VREF = VDDQ/2
SWITCHING is defined as inputs changing
between HIGH and LOW every other clock cycle
(once per two clocks) for address and control sig-
nals
Switching is defined as inputs changing between
HIGH and LOW every other data transfer (once
per clock) for DQ signals not including masks or
strobes
IDD7 Conditions
Table 13, IDD7: Operating Current, specifies detailed
timing requirements for IDD7. Changes will be
required if timing parameter changes are made to the
specification.
NOTE:
All device banks are being interleaved at minimum tRC (IDD) without violating tRRD (IDD) using a burst length of 4. Con-
trol and address bus inputs are STABLE during DESELECTs. IOUT = 0mA.
Table 11:
Input AC Logic Levels
All voltages referenced to VSS
PARAMETER
SYMBOL
MIN
MAX
UNITS
NOTES
Input High (Logic 1) Voltage
VIH(AC)VREF + 250
-
mV
Input Low (Logic 0) Voltage
VIL(AC)–
VREF - 250
mV
Table 12:
General IDD Parameters
IDD PARAMETER
-53E
-40E
UNITS
CL (IDD)
43
tCK
tRCD (IDD)
15
ns
tRC (IDD)
60
ns
tRRD (IDD)
7.5
ns
tCK (IDD)
3.75
5
ns
tRAS MIN (IDD)
45
ns
tRAS MAX (IDD)
70,000
ns
tRP (IDD)
15
ns
tRFC (IDD)
512MB
75
ns
1GB
105
ns
2GB
127.5
ns
Table 13:
IDD7: Operating Current
All Bank Interleave Read operation; legend: A = active; RA = read auto precharge; D = deselect
SPEED GRADE
IDD7 TIMING PATTERNS
-53E
A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D D
-40E
A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D D
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相關代理商/技術參數(shù) |
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| MT18HTF12872JDY-667F1D4 | 制造商:Micron Technology Inc 功能描述:1GB 128MX72 DDR2 SDRAM MODULE COMMERCIAL PBF DIMM 1.8V FULLY - Bulk |
| MT18HTF12872M2DY-667F1B4 | 制造商:Micron Technology Inc 功能描述:1GB 128MX72 DDR2 SDRAM MODULE PBF DIMM 1.8V FULLY BUFFERED - Trays |
| MT18HTF12872M2DY-667F1B5 | 制造商:Micron Technology Inc 功能描述:1GB 128MX72 DDR2 SDRAM MODULE CUSTOM 1.8V FULLY BUFFERED - Trays |
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| MT18HTF12872M3Y-53EF1 | 制造商:Micron Technology Inc 功能描述:1GB 128MX72 DDR2 SDRAM MODULE COMMERCIAL CUSTOM 1.8V REGISTE - Bulk |
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