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參數(shù)資料
| 型號： | MT16LSDT464A |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 4 Meg x 64 SDRAM DIMMs(4M x 64同步動態(tài)RAM,雙列直插存儲器模塊) |
| 中文描述： | 4梅格× 64 SDRAM的內(nèi)存插槽（4米× 64同步動態(tài)內(nèi)存，雙列直插存儲器模塊） |
| 文件頁數(shù)： | 2/19頁 |
| 文件大?。?/td> | 257K |
| 代理商： | MT16LSDT464A |
2, 4 Meg x 64 SDRAM DIMMs
ZM02.p65 – Rev. 6/98
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1998, Micron Technology, Inc.
2
2, 4 MEG x 64
SDRAM DIMMs
OBSOLETE
PART NUMBERS
PART NUMBER
MT8LSDT264AG-10B_
MT8LSDT264AG-662_
MT16LSDT464AG-10B_
MT16LSDT464AG-662_
CONFIGURATION SYSTEM BUS SPEED
2 Meg x 64
2 Meg x 64
4 Meg x 64
4 Meg x 64
100 MHz
66 MHz
100 MHz
66 MHz
NOTE
: All part numbers end with a two-place code (not shown),
designating component and PCB revisions. Consult
factory for current revision codes. Example:
MT8LSDT264AG-10BD2.
GENERAL DESCRIPTION
The MT8LSDT264A and MT16LSDT464A are high-speed
CMOS, dynamic random-access, 16MB and 32MB memo-
ries organized in a x64 configuration. These modules use
SDRAMs that are internally configured as dual memory
arrays with a synchronous interface (all signals are regis-
tered on the positive edge of the clock signals CK0-CK3).
Read and write accesses to the SDRAM module are burst
oriented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an AC-
TIVE command, which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank and
row to be accessed (BA0 selects the bank; A0-A10 select the
row). The address bits registered coincident with the READ
or WRITE command are used to select the starting column
location for the burst access.
The modules provide for programmable READ or WRITE
burst lengths of 1, 2, 4 or 8 locations, or full page, with a burst
terminate option. An AUTO PRECHARGE function may
be enabled to provide a self-timed row precharge that is
initiated at the end of the burst sequence.
The modules use an internal pipelined architecture to
achieve high-speed operation. This architecture is compat-
ible with the 2
n
rule of prefetch architectures, but it also
allows the column address to be changed on every clock
cycle to achieve a high-speed, fully random access.
Precharging one bank while accessing the alternate bank
will hide the PRECHARGE cycles and provide seamless,
high-speed, random-access operation.
The modules are designed to operate in 3.3V, low-power
memory systems. An auto refresh mode is provided, along
with a power-saving, power-down mode. All inputs and
outputs are LVTTL-compatible.
SDRA M modules offer substantial advances in
DRAM operating performance, including the ability to
synchronously burst data at a high data rate with automatic
column-address generation, the ability to interleave be-
tween internal banks in order to hide precharge time and
the capability to randomly change column addresses on
each clock cycle during a burst access. For more information
regarding the SDRAM operation, refer to the 16Mb: x4, x8
SDRAM data sheet.
SERIAL PRESENCE-DETECT OPERATION
This module incorporates serial presence-detect (SPD).
The SPD function is implemented using a 2,048-bit EEPROM.
This nonvolatile storage device contains 256 bytes. The first
128 bytes can be programmed by Micron to identify the
module type and various SDRAM organizations and tim-
ing parameters. The remaining 128 bytes of storage are
available for use by the customer. System READ/ WRITE
operations between the master (system logic) and the slave
EEPROM device (DIMM) occur via a standard IIC bus using
the DIMM’s SCL (clock) and SDA (data) signals, together
with SA(2:0), which provide eight unique DIMM/ EEPROM
addresses.
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