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參數(shù)資料
| 型號： | MT16LSDT464A |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 4 Meg x 64 SDRAM DIMMs(4M x 64同步動態(tài)RAM,雙列直插存儲器模塊) |
| 中文描述： | 4梅格× 64 SDRAM的內存插槽（4米× 64同步動態(tài)內存，雙列直插存儲器模塊） |
| 文件頁數(shù)： | 16/19頁 |
| 文件大?。?/td> | 257K |
| 代理商： | MT16LSDT464A |
2, 4 Meg x 64 SDRAM DIMMs
ZM02.p65 – Rev. 6/98
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1998, Micron Technology, Inc.
16
2, 4 MEG x 64
SDRAM DIMMs
OBSOLETE
NOTES
1. All voltages referenced to V
SS
.
2. This parameter is sampled. V
DD
= +3.3V; f = 1 MHz.
3. I
CC
is dependent on output loading and cycle rates.
Specified values are obtained with minimum cycle
time and the outputs open.
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to indicate
cycle time at which proper operation over the full
temperature range (0
°
C
≤
T
A
≤
70
°
C) is ensured.
6. An initial pause of 100
μ
s is required after power-up,
followed by two AUTO REFRESH commands, before
proper device operation is ensured. The two AUTO
REFRESH command wake-ups should be repeated
any time the
t
REF refresh requirement is exceeded.
7. AC characteristics assume
t
T = 1ns.
8. In addition to meeting the transition rate specifica-
tion, the clock and CKE must transit between V
IH
and
V
IL
(or between V
IL
and V
IH
) in a monotonic manner.
9. Outputs measured at 1.5V with equivalent load:
15. Timing actually specified by
t
WR plus
t
RP; clock(s)
specified as a reference only at minimum cycle rate.
16. Timing actually specified by
t
WR.
17. Required clocks are specified by JEDEC functionality
and are not dependent on any timing parameter.
18. The I
CC
current will decrease as the CAS latency is
reduced. This is because the maximum cycle rate is
slower as the CAS latency is reduced.
19. Address transitions an average of one transition every
30ns (20ns on -10B).
20. CLK must be toggled a minimum of two times during
this period.
21. Based on
t
CK = 100 MHz for -10B and 66 MHz for
-662.
22. 16MB module values will be half of those shown.
23. The SPD EEPROM WRITE cycle time (
t
WRC) is the
time from a valid stop condition of a write sequence
to the end of the EEPROM internal erase/ program
cycle. During the WRITE cycle, the EEPROM bus
interface circuit is disabled, SDA remains HIGH due
to the pull-up resistor, and the EEPROM does not
respond to its slave address.
24. It is recommended that the DRAM controller use two
clocks for
t
WR to support future design requirements.
25. V
IH
overshoot: V
IH
(MAX) = V
DD
+ 2V for a pulse
width
≤
10ns, and the pulse width cannot be greater
than one third of the cycle rate. V
IL
undershoot: V
IL
(MIN) = -2V for a pulse width
≤
10ns, and the pulse
width cannot be greater than one third of the cycle
rate.
26. 16MB module values will be half of those shown.
27. Auto precharge mode only.
28. Precharge mode only.
29. JEDEC and PC100 specify three clocks.
30. These five parameters vary between speed grades and
define the differences between the -8 SDRAM speeds:
-8A, -8B, -8C, -8D and -8E. All other -8 timing
parameters remain constant.
Q
50pF
10.
t
HZ defines the time at which the output achieves the
open circuit condition; it is not a reference to V
OH
or
V
OL
. The last valid data element will meet
t
OH before
going High-Z.
11. AC timing tests have V
IL
= 0V and V
IH
= 3V, with
timing referenced to 1.5V crossover point.
12. Other input signals are allowed to transition no more
than once in any 30ns period (20ns on -10B) and are
otherwise at valid V
IH
or V
IL
levels.
13. I
CC
specifications are tested after the device is
properly initialized.
14. Timing actually specified by
t
CKS; clock(s) specified
as a reference only at minimum cycle rate.
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