
MSP430F20x3
MSP430F20x2
MSP430F20x1
SLAS491H
– AUGUST 2005 – REVISED AUGUST 2011
Table 20. Port P1 (P1.4 to P1.7) Pin Functions, MSP430F20x1
CONTROL BITS / SIGNALS(2)
PIN NAME (P1.x)
x
FUNCTION(1)
P1DIR.x
P1SEL.x
CAPD.x
JTAG Mode
P1.4(3) input/output
0/1
0
N/A
0
1
0
P1.4/SMCLK/CA4/TCK
4
SMCLK
1
0
CA4(4)
X
1
0
TCK(5)
X
1
P1.5(3) input/output
0/1
0
N/A
0
1
0
P1.5/TA0/CA5/TMS
5
Timer_A2.TA0
1
0
CA5(4)
X
1
0
TMS(5)
X
1
P1.6(3) input/output
0/1
0
N/A
0
1
0
P1.6/TA1/CA6/TDI
6
Timer_A2.TA1
1
0
CA6(4)
X
1
0
TDI(5)
X
1
P1.7(3) input/output
0/1
0
N/A
0
1
0
P1.7/CAOUT/CA7/TDO/TDI
7
CAOUT
1
0
CA7(4)
X
1
0
TDO/TDI(5)(6)
X
1
(1)
N/A = Not available or not applicable
(2)
X = Don
't care
(3)
Default after reset (PUC/POR)
(4)
Setting the CAPD.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying
analog signals. Selecting the CAx input pin to the comparator multiplexer with the P2CAx bits automatically disables the input buffer for
that pin, regardless of the state of the associated CAPD.x bit.
(5)
In JTAG mode the internal pullup/down resistors are disabled.
(6)
Function controlled by JTAG
Copyright
2005–2011, Texas Instruments Incorporated
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