參數(shù)資料
型號(hào)： MSP430C336IPJM
廠商： TEXAS INSTRUMENTS INC
元件分類(lèi)： 微控制器/微處理器
英文描述： 16-BIT, MROM, 3.8 MHz, RISC MICROCONTROLLER, PQFP100
封裝： PLASTIC, MS-022, QFP-100
文件頁(yè)數(shù)： 9/42頁(yè)
文件大?。?/td> 637K
代理商： MSP430C336IPJM
MSP430C33x, MSP430P337A
MIXED SIGNAL MICROCONTROLLERS
SLAS227A – OCTOBER 1999 – REVISED JUNE 2000
17
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
absolute maximum ratings
Supply voltage range, between: VCC terminals
– 0.3 V to 0.3 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VSS terminals
– 0.3 V to 0.3 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range to any VSS terminal: VCC1
– 0.3 V to 6 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VCC2
– 0.3 V to 6 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range to any terminal (referenced to VSS)
–0.3 V to VCC + 0.3 V
. . . . . . . . . . . . . . . . . . . . . . . . . .
Diode current at any device terminal
±2 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg: Unprogrammed device
– 55
°C to 150°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Programmed device
– 40
°C to 85°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE: All voltages referenced to VSS.
Common Lines COM0 to COM3, Segment Lines S0 to S29
Output Drivers O2 to O29
VCC1
VSS1
J/X
T/B
A/U
G/F
VCC1
VSS1
Core Logic With
Core CPU, System, JTAG/Test,
All Peripheral Modules
Terminal of Timer/Port
VCC1
VSS1
Input Buffers and Output Drivers of Port P0–P4
VSS2
VCC2
(see Note A)
(see Note B)
Substrate and Ground Potential For Input Inverters/Buffers
VSS2
VSS1
NOTES: A. Ground potential for all port output drivers and input terminals, excluding first inverter/buffer
B. Ground potential for entire device core logic and peripheral modules
VSS3
Figure 2. Supply Voltage Interconnection
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