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MSP430C33x, MSP430P337A
MIXED SIGNAL MICROCONTROLLERS
SLAS227A – OCTOBER 1999 – REVISED JUNE 2000
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
operation modes and interrupts (continued)
Table 3. Interrupt Functions and Addresses
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM INTERRUPT
WORD ADDRESS
PRIORITY
Power up, external reset, watchdog
WDTIFG
Reset
0FFFEh
15, highest
NMI,
Oscillator fault
NMIIFG (see Notes 2 and 4)
OFIFG (see Notes 2 and 5)
Non-maskable
(Non)-maskable
0FFFCh
14
Dedicated I/O P0.0
P0IFG.0
Maskable
0FFFAh
13
Dedicated I/O P0.1 or 8-Bit Timer/Counter
P0IFG.1
Maskable
0FFF8h
12
Maskable
0FFF6h
11
Watchdog Timer
WDTIFG
Maskable
0FFF4h
10
Timer_A
CCIFG0 (see Note 3)
Maskable
0FFF2h
9
Timer_A
TAIFG (see Note 3)
Maskable
0FFF0h
8
UART receive
URXIFG
Maskable
0FFEEh
7
UART transmit
UTXIFG
Maskable
0FFECh
6
0FFEAh
5
Timer/Port
RC1FG, RC2FG, EN1FG
Maskable
0FFE8h
4
Timer/Port
,,
(see Note 3)
Maskable
0FFE8h
4
I/O port P2
P2IFG.07 (see Note 2)
Maskable
0FFE6h
3
I/O port P1
P1IFG.07 (see Note 2)
Maskable
0FFE4h
2
Basic Timer1
BTIFG
Maskable
0FFE2h
1
I/O port P0.2 – P0.7
P0IFG.27 (see Note 2)
Maskable
0FFE0h
0, lowest
NOTES:
2. Multiple source flags
3. Interrupt flags are located in the individual module registers.
4. Non-maskable : neither the individual or the general interrupt enable bit will disable an interrupt event.
5. (Non)-maskable: the individual interrupt enable bit can disable an interrupt event, but the general interrupt enable bit cannot.
special function registers
Most interrupt and module enable bits are collected into the lowest address space. Special function register bits
that are not allocated to a functional purpose are not physically present in the device. Simple software access
is provided with this arrangement.
interrupt enable 1 and 2
76
5
4
0
P0IE.1
OFIE
WDTIE
32
1
P0IE.0
rw-0
Address
0h
WDTIE:
Watchdog Timer interrupt enable signal
OFIE:
Oscillator fault interrupt enable signal
P0IE.0:
Dedicated I/O P0.0 interrupt enable signal
P0IE.1:
P0.1 or 8-Bit Timer/Counter, RXD interrupt enable signal
76
5
4
0
TPIE
UTXIE
URXIE
rw-0
32
1
rw-0
Address
01h
BTIE
URXIE:
USART receive interrupt enable signal
UTXIE:
USART transmit interrupt enable signal
TPIE:
Timer/Port interrupt enable signal
BTIE:
Basic Timer1 interrupt enable signal