參數(shù)資料
型號: MSP430C325IPG
廠商: TEXAS INSTRUMENTS INC
元件分類: 微控制器/微處理器
英文描述: 16-BIT, OTPROM, 3.3 MHz, RISC MICROCONTROLLER, PQFP64
封裝: QFP-64
文件頁數(shù): 8/35頁
文件大小: 511K
代理商: MSP430C325IPG
MSP430C32x, MSP430P325A
MIXED SIGNAL MICROCONTROLLER
SLAS219B MARCH 1999 REVISED MARCH 2000
16
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
input frequency Port 0: P0.1; Timer/Port: CIN, TP0.5
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
f(IN)
Input frequency
DC
f(system)
MHz
t
or t
High level or low level time
P0.x, CIN, TP.5
3 V
300
ns
t(H) or t(L)
High level or low level time
P0.x, CIN, TP.5
5 V
125
ns
output frequency
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fXBUF
XBUF,
CL = 20 pF
f(system)
MHz
XBUF
C
20 F
fMCLK = 1.1 MHz
40%
60%
tXdc
Duty cycle of O/P frequency
XBUF, CL = 20 pF,
VCC = 3 V/5 V
fXBUF = fACLK
35%
65%
Xdc
yy
q
y
VCC = 3 V/5 V
fXBUF = fACLK/n
50%
external interrupt timing
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t(int)
Port P0: External trigger signal for the
interrupt flag (see Notes 13 and 14)
1.5
cycle
NOTES: 13. The external signal sets the interrupt flag every time t(int) is met. It may be set even with trigger signals shorter than t(int). The
conditions to set the flag must be met independently of this timing constraint. Input frequency (t(int)) is defined in MCLK cycles.
14. The external signal needs additionally a timing resulting from the maximum input frequency constraint.
RAM
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VRAMh
CPU halted (see Note 15)
1.8
V
NOTE 15: This parameter defines the minimum supply voltage when the data in the program memory RAM remains unchanged. No program
execution should take place during this supply voltage condition.
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