參數(shù)資料
型號： MSP430C325IPG
廠商： TEXAS INSTRUMENTS INC
元件分類： 微控制器/微處理器
英文描述： 16-BIT, OTPROM, 3.3 MHz, RISC MICROCONTROLLER, PQFP64
封裝： QFP-64
文件頁數(shù)： 13/35頁
文件大小： 511K
代理商： MSP430C325IPG
MSP430C32x, MSP430P325A
MIXED SIGNAL MICROCONTROLLER
SLAS219B MARCH 1999 REVISED MARCH 2000
20
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
current source (ADC)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V(Rext)
Voltage, (Rext)
V(Rext) = V(SVCC) V(RI),
I(RI) = 6 mA,
VCC = 3 V/5 V,
0.246
×
V(SVCC)
0.249
×
V(SVCC)
0.252
×
V(SVCC)
V
R(ext)
External resistor
VCC = 3 V/5 V
95
1600
Ω
VA0..A3 = 0 .. 0.4
× V(SVCC), IS =
V(Rext)/R(ext) = 1 mA
VCC = 3 V,
1
μA
ΔI
Load compliance
VA0..A3 = 0 .. 0.4
× V(SVCC),
IS = V(Rext)/R(ext) = 6 mA
VCC = 3 V,
3.2
μA
ΔIS
Load compliance
VA0..A3 = 0 .. 0.5
× V(SVCC)
IS = V(Rext)/R(ext)= 1 mA
VCC = 5 V,
1.5
μA
VA0..A3 = 0 .. 0.5
× V(SVCC)
IS = V(Rext)/R(ext)= 6 mA
VCC = 5 V,
3.2
μA
A/D converter (f(ADCLK) = 1 MHz)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Resolution
12 + 2
bits
f
Conversion frequency
f
12-bit conversion
V
3 V/5 V
0.1
1.5
MHz
f(con)
Conversion frequency
f(con) = f(ADCLK)
12+2-bit conversion
VCC = 3 V/5 V
0.14
1.5
MHz
f
Conversion cycles
f
/N
12-bit conversion
V
3 V/5 V
96
cycles of
f(concyc)
Conversion cycles
f(ADCLK) = f(MCLK)/N
12+2-bit conversion
VCC = 3 V/5 V
132
cycles of
ADCLK
LSB Voltage
VCC = 3 V/5 V
0.000061
×VSVCC
V
INL1
0
≤ DDV ≤ 127
VCC = 3 V/5 V
2
LSB
INL2
Integral nonlinearity,
128
≤ DDV ≤ 255
VCC = 3 V/5 V
3
LSB
INL3
Integral nonlinearity,
(see Note 18)
256
≤ DDV ≤ 2047
VCC = 3 V/5 V
7
LSB
INL4
2048
≤ DDV ≤ 4095
VCC = 3 V/5 V
10
LSB
DNL
Differential nonlinearity,
(see Note 19)
VCC = 3 V/5 V
1
LSB
dN/dT
Temperature stability
V(Rext)/R(ext) = 6mA, Range A
V
3 V/5 V
0.008
LSB/
°C
dN/dT
Temperature stability
Range B
VCC = 3 V/5 V
0.015
LSB/
°C
dN/dV(SVCC)
V(SVCC)rejection ratio
Range A, B, V(Rext)/R(ext) = 1 mA,
SVCC ±10%
VCC = 3 V/5 V
1.25
LSB/V
Range A
VCC = 3 V/5 V
1.2
0.49
0.24
% FSRA
(see Note 17)
Conversion offset 12 bit analog input to
Range B
VCC = 3 V/5 V
1.7
0.6
0.49
% FSRB
(see Note 17)
Conversion offset 12 bit analog input to
digital value (see Note 16)
Range C
VCC = 3 V/5 V
1.8
0.6
% FSRC
(see Note 17)
Range D
VCC = 3 V/5 V
1.7
0.6
0.49
% FSRD
(see Note 17)
Conversion offset 14 bit analog input to
digital value (see Note 16)
Range ABCD
VCC = 3 V/5 V
0.27
0.06
0.13
%FSRABCD
(see Note 17)
Slope 12 bit
VCC = 3 V/5 V
0.9925
1
1.0075
Slope 14 bit
VCC = 3 V/5 V
0.9982
1
1.0018
C(IN)
Input capacitance
VCC = 3 V/5 V
40
45
pF
R(SIN)
Serial input resistance
VCC = 3 V/5 V
2
k
Ω
NOTES: 16. Offset referred to full scale 12/14 bit
17. FSRx: full scale range, separate for the four 12-bit ranges and the 14-bit (12+2) range.
18. DDV is short form of delta digital value. The DDV is a span of conversion results. It is assumed that the conversion is of 12 bit not
12+2 bit.
19. DNL is valid for all 12-bit ranges and the 14-bit (12+2) range.
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