參數(shù)資料
型號(hào): MSP34X5G
廠商: Electronic Theatre Controls, Inc.
英文描述: MSP 34x5G Multistandard Sound Processor Family
中文描述: 中型34x5G多標(biāo)準(zhǔn)聲音處理器系列
文件頁(yè)數(shù): 78/98頁(yè)
文件大小: 1541K
代理商: MSP34X5G
MSP 34x5G
PRELIMINARY DATA SHEET
78
Micronas
6.2. DSP Write and Read Registers for Manual/Compatibility Mode
Table 6
2:
Demodulator Read Registers; Subaddress: 11
hex
; these registers are not writable!
Demodulator
Read Registers
Address
(hex)
MSP-
Version
Description
Page
C_AD_BITS
00 23
3415,
3455
NICAM-Sync bit, NICAM-C-Bits, and three LSBs of additional data bits
87
ADD_BITS
00 38
NICAM: bit [10:3] of additional data bits
87
CIB_BITS
00 3E
NICAM: CIB1 and CIB2 control bits
87
ERROR_RATE
00 57
NICAM error rate, updated with 182 ms
88
PLL_CAPS
02 1F
Not for customer use.
88
AGC_GAIN
02 1E
Not for customer use.
88
Table 6
3:
DSP-Write Registers; Subaddress: 12
hex
, all registers are readable as well
Write Register
Address
(hex)
Bits
Operational Modes and Adjustable Range
Reset
Mode
Page
Volume SCART1 channel: Ctrl. mode
00 07
[7:0]
[Linear mode / logarithmic mode]
00
hex
89
FM Fixed Deemphasis
00 0F
[15:8]
[50
μ
s, 75
μ
s, J17, OFF]
50
μ
s
89
FM Adaptive Deemphasis
[7:0]
[OFF, WP1]
OFF
89
Identification Mode
00 15
[7:0]
[B/G, M]
B/G
90
FM DC Notch
00 17
[7:0]
[ON, OFF]
ON
90
Table 6
4:
DSP Read Registers; Subaddress: 13
hex
, all registers are not writable
Additional Read
Registers
Address
(hex)
Bits
Output Range
Page
Stereo detection register for
A2 Stereo Systems
00 18
[15:8]
[80
hex
... 7F
hex
]
8 bit two
s complement
90
DC level readout FM1/Ch2-L
00 1B
[15:0]
[8000
hex
... 7FFF
hex
]
16 bit two
s complement
90
DC level readout FM2/Ch1-R
00 1C
[15:0]
[8000
hex
... 7FFF
hex
]
16 bit two
s complement
90
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