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參數(shù)資料
| 型號： | MSP34X5G |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | MSP 34x5G Multistandard Sound Processor Family |
| 中文描述： | 中型34x5G多標(biāo)準(zhǔn)聲音處理器系列 |
| 文件頁數(shù)： | 23/98頁 |
| 文件大?。?/td> | 1541K |
| 代理商： | MSP34X5G |
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PRELIMINARY DATA SHEET
MSP 34x5G
Micronas
23
3.3.2.4. Write Registers on I
2
C Subaddress 10
hex
Table 3
–
9:
Write registers on I
2
C subaddress 10
hex
Register
Address
Function
Name
00 20
hex
STANDARD SELECTION Register
Defines TV-Sound or FM-Radio Standard
bit[15:0]
00 01
hex
00 02
hex
...
00 60
hex
start Automatic Standard Detection
MSP Standard Codes (see Table 3
–
7)
STANDARD_SEL
00 30
hex
MODUS Register
Preference in Automatic Standard Detection:
bit[15]
0
undefined, must be 0
detected 4.5 MHz carrier is interpreted as:
1)
standard M (Korea)
standard M (BTSC)
standard M (Japan)
chroma carrier (M/N standards are ignored)
detected 6.5 MHz carrier is interpreted as:
1)
standard L (SECAM)
standard D/K1, D/K2, D/K3, or D/K NICAM
bit[14:13]
0
1
2
3
bit[12]
0
1
General MSP 34x5G Options
bit[11:8]
0
undefined, must be 0
bit[7]
0/1
active/tristate state of audio clock output pin
AUD_CL_OUT
I
2
S word strobe alignment
WS changes at data word boundary
WS changes one clock cycle in advance
master/slave mode of I
2
S interface (must be set to 0
(= Master) in case of NICAM mode)
active/tristate state of I
2
S output pins
bit[6]
0
1
bit[5]
0/1
bit[4]
0/1
bit[3]
state of digital output pins D_CTR_I/O_0 and _1
active: D_CTR_I/O_0 and _1 are output pins
(can be set by means of the ACB register.
see also: MODUS[1])
tristate: D_CTR_I/O_0 and _1 are input pins
(level can be read out of STATUS[4,3])
0
1
bit[2]
0
undefined, must be 0
bit[1]
0/1
disable/enable STATUS change indication by means of
the digital I/O pin D_CTR_I/O_1
Necessary condition: MODUS[3] = 0 (active)
bit[0]
0/1off/on: Automatic Sound Select
MODUS
1)
Valid at the next start of Automatic Standard Detection.
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