參數(shù)資料
型號(hào): MSP3465G
廠商: Electronic Theatre Controls, Inc.
英文描述: MSP 34x5G Multistandard Sound Processor Family
中文描述: 中型34x5G多標(biāo)準(zhǔn)聲音處理器系列
文件頁(yè)數(shù): 16/98頁(yè)
文件大?。?/td> 1541K
代理商: MSP3465G
MSP 34x5G
PRELIMINARY DATA SHEET
16
Micronas
3.1.2. Description of CONTROL Register
3.1.3. Protocol Description
Write to DSP or Demodulator
Read from DSP or Demodulator
Write to Control Register
Read from Control Register
Note:
S =
I
2
C-Bus Start Condition from master
I
2
C-Bus Stop Condition from master
ACK = Acknowledge-Bit: LOW on I2C_DA from slave (= MSP, light gray) or master (= controller, dark gray)
NAK = Not Acknowledge-Bit: HIGH on I2C_DA from master (dark gray) to indicate
End of Read
or from MSP indicating internal error state
Wait = I
2
C-Clock line is held low, while the MSP is processing the I
2
C command.
This waiting time is max. 1 ms
P =
Table 3
3:
CONTROL as a Write Register
Name
Subaddress
Bit[15] (MSB)
Bits[14:0]
CONTROL
00
hex
1 : RESET
0 : normal
0
Table 3
4:
CONTROL as a Read Register
Name
Subaddress
Bit
Bit
CONTROL
00
hex
RESET status after last reading of
CONTROL:
0 : no reset occured
1 : reset occured
Internal hardware status:
0 : no error occured
1 : internal error occured
not of interest
Reading of CONTROL will reset the bits[15,14] of CONTROL. After Power-on,
bit[15] of CONTROL
will be set; it must be
read once to be reset.
S
write
device
address
Wait
ACK
sub-addr ACK addr-byte
high
ACK addr-byte
low
ACK data-byte
high
ACK data-byte
low
ACK
P
S
write
device
address
Wait
ACK
sub-addr ACK addr-byte
high
ACK addr-byte
low
ACK
S
read
device
address
Wait
ACK data-byte-
high
ACK data-byte
low
NAK
P
S
write
device
address
Wait
ACK
sub-addr ACK data-byte
high
ACK data-byte
low
ACK
P
S
write
device
address
Wait
ACK
00hex
ACK
S
read
device
address
Wait
ACK data-byte-
high
ACK data-byte
low
NAK
P
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