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參數(shù)資料
| 型號(hào)： | MSP3465G |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | MSP 34x5G Multistandard Sound Processor Family |
| 中文描述： | 中型34x5G多標(biāo)準(zhǔn)聲音處理器系列 |
| 文件頁(yè)數(shù)： | 15/98頁(yè) |
| 文件大?。?/td> | 1541K |
| 代理商： | MSP3465G |
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PRELIMINARY DATA SHEET
MSP 34x5G
Micronas
15
3. Control Interface
3.1. I
2
C Bus Interface
The MSP 34x5G is controlled via the I
2
C bus slave
interface.
The IC is selected by transmitting one of the
MSP 34x5G device addresses. In order to allow up to
three MSP ICs to be connected to a single bus, an
address select pin (ADR_SEL) has been implemented.
With ADR_SEL pulled to high, low, or left open, the
MSP 34x5G responds to different device addresses. A
device address pair is defined as a write address and a
read address (see Table 3
–
1).
Writing
is done by sending the write device address,
followed by the subaddress byte, two address bytes,
and two data bytes.
Reading
is done by sending the write device address,
followed by the subaddress byte and two address
bytes. Without sending a stop condition, reading of the
addressed data is completed by sending the device
read address and reading two bytes of data.
Refer to Section 3.1.3. for the I
2
C bus protocol and to
Section 3.4.
“
Programming Tips
”
on page 37
for pro-
posals of MSP 34x5G I
2
C telegrams. See Table 3
–
2
for a list of available subaddresses.
Besides the possibility of hardware reset, the MSP can
also be reset by means of the RESET bit in the CON-
TROL register by the controller via I
2
C bus.
Due to the architecture of the MSP 34x5G, the IC can-
not react immediately to an I
2
C request. The typical
response time is about 0.3 ms. If the MSP cannot
accept another byte of data (e.g. while servicing an
internal interrupt), it holds the clock line I2C_CL low to
force the transmitter into a wait state. The I
2
C Bus
Master must read back the clock line to detect when
the MSP is ready to receive the next I
2
C transmission.
The positions within a transmission where this may
happen are indicated by
’
Wait
’
in Section 3.1.3. The
maximum wait period of the MSP during normal opera-
tion mode is less than 1 ms.
3.1.1. Internal Hardware Error Handling
In case of any hardware problems (e.g. interruption of
the power supply of the MSP), the MSP
’
s wait period is
extended to 1.8 ms. After this time period elapses, the
MSP releases data and clock lines.
Indication and solving the error status:
To indicate the error status, the remaining acknowl-
edge bits of the actual I
2
C-protocol will be left high.
Additionally, bit[14] of CONTROL is set to one. The
MSP can then be reset via the I
2
C bus by transmitting
the RESET condition to CONTROL.
Indication of reset:
Any reset, even caused by an unstable reset line etc.,
is indicated in bit[15] of CONTROL.
A general timing diagram of the I
2
C bus is shown in
Fig. 4
–
27 on page 61.
Table 3
–
1:
I
2
C Bus Device Addresses
ADR_SEL
Low
(connected to DVSS)
High
(connected to DVSUP)
Left Open
Mode
Write
Read
Write
Read
Write
Read
MSP device address
80
hex
81
hex
84
hex
85
hex
88
hex
89
hex
Table 3
–
2:
I
2
C Bus Subaddresses
Name
Binary Value
Hex Value
Mode
Function
CONTROL
0000 0000
00
Read/Write
Write: Software reset of MSP (see Table 3
–
3)
Read: Hardware error status of MSP
WR_DEM
0001 0000
10
Write
write address demodulator
RD_DEM
0001 0001
11
Write
read address demodulator
WR_DSP
0001 0010
12
Write
write address DSP
RD_DSP
0001 0011
13
Write
read address DSP
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