參數(shù)資料
型號(hào): MSM82C55A-2GS-2K
廠商: LAPIS SEMICONDUCTOR CO LTD
元件分類(lèi): 微控制器/微處理器
英文描述: 24 I/O, PIA-GENERAL PURPOSE, PQFP44
封裝: 0.80 MM PITCH, PLASTIC, QFP-44
文件頁(yè)數(shù): 4/27頁(yè)
文件大小: 207K
代理商: MSM82C55A-2GS-2K
11/26
Semiconductor
MSM82C55A-2RS/GS/VJS
OPERATIONAL DESCRIPTION
Control Logic
Operations by addresses and control signals, e.g., read and write, etc. are as shown in the table
below:
Setting of Control Word
The control register is composed of 7-bit latch circuit and 1-bit flag as shown below.
D0
Definition of input/
output of low order
4 bits of port C.
0 = Output
1 = Input
Definition of input/
output of 8 bits of
port B.
0 = Output
1 = Input
Mode definition of
group B.
0 = Mode 0
1 = Mode 1
Definition of input/
output of high order
4 bits of port C.
0 = Output
1 = Input
Definition of input/
output of 8 bits of
port A.
0 = Output
1 = Input
Mode definition of group A.
D1
D2
D3
D4
D5
D6
D7
D6 D5
Mode
0
Mode 0
0
1
Mode 1
1
Mode 2
Control word Identification flag
When set to 0, it becomes
the control word for bit set/
reset.
Group A Control Bits
Group B Control Bits
Be sure to set 1 for the control word
to define a mode and input/output.
CS
Input
0
Port A
Data Bus
00
Control
1
0
Others
10
A0
0
1
WR
1
0
1
Operaiton
Operation
A1
Output
0
1
0
RD
00
11
0
10
01
0
00
10
1
10
00
1
1
Port B
Data Bus
Port C
Data Bus
Data Bus
Port A
Data Bus
Port B
Data Bus
Port C
Data Bus
Control Register
Illegal Condition
Data bus is in the high impedance status.
相關(guān)PDF資料
PDF描述
MSM82C55A-2RS 24 I/O, PIA-GENERAL PURPOSE, PDIP40
MSM82C55A-2VJS 24 I/O, PIA-GENERAL PURPOSE, PQCC44
MSM82C59A-2GS-K 80C85AH; 80C86A; 80C88A COMPATIBLE, INTERRUPT CONTROLLER, PDSO32
MSM82C84A-2GS-K 8 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO24
MSM82C84A-2JS OTHER CLOCK GENERATOR, PQCC20
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