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參數(shù)資料
| 型號： | MSM8128GXLMB-10 |
| 元件分類： | SRAM |
| 英文描述： | 128K X 8 STANDARD SRAM, 100 ns, CDFP32 |
| 封裝： | DFP-32 |
| 文件頁數(shù)： | 7/10頁 |
| 文件大小： | 224K |
| 代理商： | MSM8128GXLMB-10 |
MSM8128 - 70/85/10/12
Issue 4.4 : February 2000
7
Low V
CC
Data Retention Timing Waveform 1
(CS1 controlled)
Low V
CC
Data Retention Timing Waveform 2
(CS2 controlled)
t
R
t
CDR
4.5V
2.2V
V
DR
4.5V
2.2V
0V
DATA RETENTION MODE
Vcc
CS1
CS1
≥
Vcc-0.2V
4.5V
4.5V
0V
DATA RETENTION MODE
Vcc
CS2
V
DR2
0.4V
t
R
t
CDR
CS2
≤
0.2V
AC Characteristics Notes
(1) A write occurs during the overlap of a low CS1, a high CS2 and a low WE. A write begins at the latest transition among
CS1 going low, CS2 going high and WE going low. A write ends at the earliest transition among CS1 going high, CS2
going low and WE going high. t
WP
is measured from the beginning of write to the end of write.
(2) t
WR
is measured from the earlier of CS1 or WE going high or CS2 going high to the end of write cycle.
(3) During this period, I/O pins are in the output state. Input signals out of phase must not be applied.
(4) If CS1 goes low simultaneously with WE going low or after WE going low, outputs remain in high impedance state.
(5) OE is continuously low. (OE=V
IL
)
(6) Dout is in the same phase as written data of this write cycle.
(7) Dout is the read data of next address.
(8) If CS1 is low and CS2 is high during this period, I/O pins are in the output state. Input signals out of phase must not be
applied to I/O pins.
(9) t
is defined as the time at which the outputs achieve the open circuit conditions and is not referenced to output voltage
levels. These parameters are sampled and not 100% tested.
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