參數(shù)資料
型號: MSM8128GXLMB-10
元件分類: SRAM
英文描述: 128K X 8 STANDARD SRAM, 100 ns, CDFP32
封裝: DFP-32
文件頁數(shù): 3/10頁
文件大?。?/td> 224K
代理商: MSM8128GXLMB-10
MSM8128 - 70/85/10/12
Issue 4.4 : February 2000
3
Operating Modes
The table below shows the logic inputs required to control the MSM8128 SRAM.
Mode
CS1
CS2
OE
WE
V
CC
Current
I/O Pin
Reference Cycle
Not Selected
1
X
X
X
I
SB1
,I
SB2
I
SB
,I
SB1
I
CC
I
CC
I
CC
High Z
Power Down
Not Selected
X
0
X
X
High Z
Power Down
Output Disable
0
1
1
1
High Z
Read
0
1
0
1
D
OUT
D
IN
Read Cycle
Write
0
1
X
0
Write Cycle
1 = V
IH
,
0 = V
IL
,
X = Don't Care
Low V
cc
Data Retention Characteristics - L Version Only
(T
A
=-55
°
C to +125
o
C)
Parameter
Symbol
Test Condition
min
typ
max
Unit
V
CC
for Data Retention
V
DR
CS1
V
CC
-0.2V, CS2
V
CC
-0.2V or
0V
CS2
0.2V. V
IN
0V
V
CC
=3.0V,V
IN
0V, CS1
V
CC
-0.2V,
CS2
V
CC
-0.2V or 0V
CS2
0.2V.
See Retention Waveform
See Retention Waveform
2.0
-
-
V
Data Retention Current
I
CCDR
-
-
-
-
700
μ
A
ns
ms
Chip Deselect to Data Retention
Operation Recovery Time
t
CDR
t
R
0
5
-
-
Notes (1) CS2 controls address buffer, WE buffer, CS1 buffer and OE buffer. If CS2 controls data retention mode,
Vin levels (WE,OE,CS1,I/O) can be in the high impedance state. If CS1 controls Data Retention mode,
CS2 must be
V
- 0.2V or 0V
CS2
0.2V. The other input levels (address, WE,OE,I/O) can be in the
high impedance state.
AC Test Conditions
Output Load
* Input pulse levels: 0V to 3.0V
* Input rise and fall times: 5ns
* Input and Output timing reference levels: 1.5V
* Output load: See Load Diagram
* V
cc
=5V±10%
166
30pF
I/O Pin
1.76V
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