參數(shù)資料
型號(hào)： MSM7583GS-BK
廠商： OKI SEMICONDUCTOR CO., LTD.
英文描述： pie/4 Shift QPSK MODEM
中文描述： 餡餅/ 4移調(diào)制調(diào)制解調(diào)器
文件頁(yè)數(shù)： 6/23頁(yè)
文件大?。?/td> 215K
代理商： MSM7583GS-BK
6/23
MSM7583
Semiconductor
SG
Internal reference voltage output.
The output voltage is about 2.0 V. A bypass capacitor should be connected between this pin
and the AGND pin. The external SG voltage, if necessary should be used via buffer.
RESET
Control register reset.
When this pin is set to "0", the register is reset to the initial value.
The reset signal input width is 200 ns or more.
PDN0, PDN1, PDN2
Inputs for power-down control.
PDN0 controls the standby/communication modes, PDN1 controls the modulator, and PDN2
controls the demodulator. Refer to Table 1 for details.
Table 1 Power Down Control
V
DD
+5 V power supply voltage.
AGND
Analog signal ground.
DGND
Digital signal ground.
AGND and DGND are not connected in the device. This pin should be tied to the AGND pin
on the PCB as close as possible from the device.
AGND and DGND should be connected as close as prossible on the PC board.
PDN2
0
All power-down.
Modulator power is off (VREF and PLL power is also off).
Demodulator power is on.
Standby Mode
PDN1
—
Modulator power is off (VREF and PLL power is on).
I and Q outputs are in a high-impedance state.
Only demodulator clock recovery block power is on.
Modulator power is on.
Only demodulator clock recovery block power is on.
Modulator power is off (VREF and PLL power is on).
I and Q outputs are in a high-impedance state.
Demodulator power is on.
Modulator power is on.
Demodulator power is on.
Mode A
Mode
PDN0
0
Function
Communication
Mode
Mode B
0
—
1
Mode C
1
0
0
Mode D
1
1
0
Mode E
1
0
1
Mode F
1
1
1
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