參數(shù)資料
型號: MSM6794
廠商: OKI SEMICONDUCTOR CO., LTD.
英文描述: LCD Driver(LCD驅(qū)動器)
中文描述: LCD驅(qū)動器(液晶驅(qū)動器)
文件頁數(shù): 19/34頁
文件大?。?/td> 195K
代理商: MSM6794
Semiconductor
19/34
MSM6794
Control register (FCR)
D7
INC
D6
WLS
D5
D4
D3
FFS
D2
D1
D0
DUTY
(1) D7 INC (Address Increment Direction)
1: X direction
0: Y direction
This bit sets the address increment direction of the display RAM. The address of the display
RAM is automatically incremented by 1 by writing data to the display data register. Writing
"1" to this bit sets the X address increment, and writing "0" to this bit sets the Y address
increment.
For details of address increment, see "X, Y Address Counter Auto Increment".
The value of this register does not change, even if the
RESET
pin is set to "L".
(2) D6 WLS (Word Length Select)
1: 6 bits
0: 8 bits
This bit selects the read/write word length to the display RAM. Writing "1" to this bit sets
read/write data to the display RAM in 6 bit units, and writing "0" to this bit sets read/write
data to the display RAM in 8 bit units. Select the word length according to the character font
to be used.
The value of this register does not change, even if the
RESET
pin is set to "L".
(3) D5 (Invalid Bit)
Writing to this bit is invalid. "0" is always read from this bit.
(4) D4 to D2 FFS (Frame Frequency Select)
This bit selects the internal clock frequency dividing ratio to the original oscillation frequency.
Correspondence between each bit and each frequency dividing ratio is shown in the table
below.
Code
0
1
2
3
4
5
6
7
D4
0
0
0
0
1
1
1
1
D3
0
0
1
1
0
0
1
1
D2
0
1
0
1
0
1
0
1
Frequency Dividing Ratio
1
1/2
1/3
1/4
1/6
1/8
TEST
TEST
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