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Semiconductor
MSM6794
Register Description
Address register (AR)
D7
D6
STBY
D5
DISP
D4
D3
HZ
D2
—
D1
Register number
D0
BUSY
SERW
(1) D7 BUSY (Busy flag)
1: busy
0: ready
This bit indicates that this IC is in internal processing. Reading/Writing display memory sets
this bit to "1". This bit becomes busy for a period of a maximum of 8 clocks by reading/writing
display memory. Registers other than this register cannot be read or written while this bit is
"1".
Setting the
RESET
pin to "L" also sets this bit to "1". This bit becomes "1" while the
RESET
pin
is "L", and becomes "0" when the
RESET
pin becomes "H". In the case of a serial interface, the
SO pin becomes high impedance if the
RESET
pin becomes "L". Therefore this bit cannot be
read during a reset period.
This bit is read only. Writing to this bit is invalid.
(2) D6 STBY (Standby)
1: standby
0: normal
This bit sets this IC to standby mode. This IC enters standby mode by writing "1" to this bit,
and returns from standby mode to normal mode by writing "0" to this bit.
This bit is set to normal status by setting the
RESET
pin to "L".
Setting this bit to standby mode in a busy state may cause a malfunction.
For details of standby mode, see "Pin status during Standby Operation and Register Status
after Cancellation".
(3) D5 DISP (Display on/off)
1: display on
0: display off
This bit sets ON/OFF of the liquid crystal display connected to this IC. Writing "1" to this bit
turns the liquid crystal display ON, and writing "0" turns it OFF. This bit is used to prevent
a random display until the initialization of the display memory after power-on.
This bit is set to display off status by setting the
RESET
pin to "L".
(4) D4 SERW (Serial Data Read/Write)
1: writing registers other than address register is invalid
0: writing all registers is valid
This bit limits writing to registers when a serial interface is used. Writing "1" to this bit disables
writing to registers other than the address register, and writing "0" enables writing to all
registers.
This bit is a command to make registers read-only when a serial interface is used. When serial
data is read from the SO pin, this pin disables writing to registers other than the address
register, even if data is input to the SI pin.
This bit is valid only when a serial interface is used. When a parallel interface is used, writing
to this bit is invalid, and "0" is always read from this bit.
This bit is set to write enable of all registers by setting the
RESET
pin to "L". This bit is
automatically reset to "0" each time the RS pin is set from "H" to "L".