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參數(shù)資料
| 型號： | MSM6542-3RS |
| 廠商： | LAPIS SEMICONDUCTOR CO LTD |
| 元件分類： | 時鐘/數(shù)據(jù)恢復(fù)及定時提取 |
| 英文描述： | 1 TIMER(S), REAL TIME CLOCK, PDIP24 |
| 封裝： | 0.600 INCH, PLASTIC, DIP-24 |
| 文件頁數(shù)： | 46/55頁 |
| 文件大?。?/td> | 361K |
| 代理商： | MSM6542-3RS |
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Semiconductor
MSM6542-01/02/03
116
[Sensing interrupts]
(a) When the DP bit is 0
Interrupt
Y
N
Another IC is
an interrupt
factor
Read CE register
Are both IRQ FLAG1
and IRQ FLAG2 bits
0 ?
Take action for
IRQ FLAG1 and
IRQ FLAG2
(b) When the DP bit is 1
Read CE register
ID on CPU side
Take action for IRQ
FLAG1 and IRQ FLAG2
Are both IRQ FLAG1
and IRQ FLAG2 bits
0 ?
IRQ FLAG0 = 0
IE on CPU side
Another IC is
an interrupt
factor
Y
N
* 1
ID: Interrupt Disable
Y
N
* 2
N
Y
* 3
IE: Interrupt
Enable
Interrupt
Read CE register
Are both IRQ FLAG1
and IRQ FLAG2 bits
0 ?
Read CE register
*1
When the IRQ FLAG
1 and
IRQFLAG
2 bits are read, they
are cleared. Restoration of
these pins to the open
output status is delayed up
to 122 s. For this reason,
the CPU is interrupt-
disabled --- the CPU cannot
accept interrupts.
*2
When the maximum delay
of 122 s described in *1
elapses, the IRA FLAG
0 bit
is set at 0.
*3
Since hardware output re-
questing an interrupt is re-
stored to the open status,
let the CPU interrupt enable.
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