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參數(shù)資料
| 型號(hào)： | MSM6542-3RS |
| 廠商： | LAPIS SEMICONDUCTOR CO LTD |
| 元件分類： | 時(shí)鐘/數(shù)據(jù)恢復(fù)及定時(shí)提取 |
| 英文描述： | 1 TIMER(S), REAL TIME CLOCK, PDIP24 |
| 封裝： | 0.600 INCH, PLASTIC, DIP-24 |
| 文件頁數(shù)： | 41/55頁 |
| 文件大?。?/td> | 361K |
| 代理商： | MSM6542-3RS |
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Semiconductor
MSM6542-01/02/03
112
Method 2 (periodic readout)
CD'
(0, d2, d1, d0)
* 2
IT/PLS1
1
MASK1
0
Read CE register
* 3
* 4
Idling
The CPU detects
an interrupt
Read CE register
IRQ FLAG1 = 1
Y
When DP is 1
When DP is 0
Idling for at least 3 s
Inhibit CPU from
accepting interrupts
Read clock registers
Idling for at least 3 s
* 5
Idling
* 6
Allow CPU to
accept interrupts
Other causes
* 7
* 8
N
* 1
Interrupt handling
routine
*5
Time required to increment the ripple
counter
*6, *7 The length of the time must be 122 s
or more because interrupt output is
delayed 122 s due to DP = 1. The
idling market *6 is provided for this
adjustment.
*8
To assure that readout is completed
before the next carry is generated, the
time required for these steps must
not be longer than the minimum set
time unit.
*1
Only for initial setting at power on
*2
The values of d2, d1, and d0 depend
on the required minimum time unit as
follows:
d2 d1 d0
When up to 1 s is required
1
0 1
When up to 1 min is required
1
1 0
When up to 10 min are required
1
1 1
*3
Dummy read to clear the IRQ FLAG
1 bit
*4
122 s when the DP bit is 1,0 s when
the DP bit is 0
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