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參數(shù)資料
| 型號： | MSM6542-03 |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | REAL TIME CLOCK WITH PERIODIC AND ALARM OUTPUT |
| 中文描述： | 實時時鐘周期和報警輸出 |
| 文件頁數(shù)： | 28/54頁 |
| 文件大?。?/td> | 378K |
| 代理商： | MSM6542-03 |
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Semiconductor
MSM6542-01/02/03
95
When an IRQ FLAG bits are read mistakenly due to external noise, particularly
erroneous read signal noise which is generated when the standby power supply
voltage is switched to the system power supply voltage or vice versa, therefore, the
IRQ FLAG bits are not cleared immediately but read at the correct times.
When 1 is written in the DP bit, the bit is immediately set at 1 except the following two
cases.
(i)
The CS
1
bit is low.
(ii)
For 62
μ
s immediately after the DP bit changes from 1 to 0.
Writing 0 in the DP bit, that is, canceling data protection is allowed only when:
(i)
Zero is written in the DP bit more than 2 ms after CS
1
changes from low to high.
(ii)
The CS
1
bit is high 11 ms after 0 is written in the DP bit.
b) CAL (D
1
) (CALendar)
This bit specifies a range in which the realtime counter is incremented. When the bit is 1,
the R-S
to R-Y
and R-W register can be incremented. When the bit is 0, the R-S
1
to R-H
10
and R-W registers can be incremented.
With the CAL bit set at 1, R-D
to R-Y
are used as realtime registers. Therefore, setting an
impossible time in these registers causes an error. For the bits marked an asterisk (*) of the
R-D
and R-MO
registers in the register table, when 1 is written, 0 is automatically set. The
alarm comparison range is specified by the A-ENABLE register.
When the CAL bit is 0, the R-D
to R-Y
registers are not incremented. They can be used as
static RAM, enabling arbitrary values to be set. The bits marked an asterisk (*) of the R-D
10
and R-MO
registers in the register table can be subject to both write and read operations.
The alarm comparison range is specified by the A-ENABLE register. However, the R-D
to
R-Y
registers are assumed to always provide a match. When these registers are used as
static RAM, they cannot be rewritten when the DP bit is 1.
CS
1
Data protection can be canceled
because CS
1
is high
0 is written
in the DPbit
DPbit
1 is written
in the DPbit
11ms
1 written in the DPbit
in this period is ignored
62μs
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