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參數(shù)資料
| 型號： | MSM6542-03 |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | REAL TIME CLOCK WITH PERIODIC AND ALARM OUTPUT |
| 中文描述： | 實時時鐘周期和報警輸出 |
| 文件頁數(shù)： | 19/54頁 |
| 文件大小： | 378K |
| 代理商： | MSM6542-03 |
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Semiconductor
MSM6542-01/02/03
86
b)
MASK
2
(D
1
)
This bit controls the alarm output each time the contents of the clock counter match the date
and time for which an alarm is set. When the bit is 0, an alarm is output from the
INTERRUPT OUT pin for the MSM6542-01/02 or the ALARM OUT pin for the MSM6542-
3. When the bit is 1, alarm output is disabled.
The relationships between causes of alarm output and the status of the MASK
bit are shown
below. (For the MSM6542-01/02, data resulting from the OR-ing of periodic output and
alarm output is output to the INTERRUPT OUT pin. For convenience, however, periodic
output is ignored in the following description.)
i)
In the alarm interrupt mode (when the IT/PLS
2
bit is 1)
The open status is entered when the IRQ FLAG
2
is read. (*1)
When the IRQ FLAG
2
is read during masking,
IRQ FLAG
2
is not cleared. (*2)
A match for an alarm is not found
because the MASK
2
bit is 1.
Open
Low level
Match for an alarm
"0"
"0"
"1"
"1"
INTERRUPT OUT (-01, -02)
ALARM OUT (-03)
MASK
2
bit
*1
When DP = 1, the open state is not entered until a certain period
passes after an interrupt is generated. (See the description of the C
E
register.)
However, when DP = 1, if the IRQ FLAG
bit is read out within
122
μ
s after an interrupt is generated, it is cleared after 122
μ
s from the
generation of the interrupt.
*2
ii)
In the alarm pulse output mode (when the IT/PLS
2
bit is 0)
When the IRQ FLAG
2
bit is set at 0, the open state is
entered without having to wait for automatic
restration
The low level is not output
because the MASK
2
bit is 1.
Open
Low level
Match for an alarm
"0"
"0"
"1"
MASK
2
bit
Automatic restoration
INTERRUPT OUT
(-01, -02)
ALARM OUT
(-03)
"1"
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