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參數(shù)資料
| 型號(hào)： | MSM63V89C |
| 廠(chǎng)商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | 1,048,576-Word x 1-Bit Solid-State Recorder Data Register(1M×1固體話(huà)音寄存器) |
| 中文描述： | 1,048,576字× 1位固態(tài)記錄器數(shù)據(jù)寄存器（1米× 1固體話(huà)音寄存器） |
| 文件頁(yè)數(shù)： | 8/10頁(yè) |
| 文件大?。?/td> | 124K |
| 代理商： | MSM63V89C |
Semiconductor
MSM63V89C
8/10
FUNCTIONAL DESCRIPTION
Serial Address Input (SAD)
Pin for inputting the start address for read/write. Address data can be input in units of 1024 words.
The 1,024 address data can be input as 10-bit (A0-A9) serial from the SAD pin.
Serial Address Strobe (
SAS
)
Pin for the clock used to store the serial address data into the internal register.
Address Transfer Strobe (
TAS
)
Input pin for setting the serial address data stored in the address register to the internal address
counter.
When the
TAS
falls, the Y address is set to address 0.
Read/Write Clock (
RWCK
)
Input pin for the data register information read/write clock.
Internal operation starts at the falling edge of
RWCK
. The information in the data register is output
to the DOUT pin in the read mode, and the information at the DIN pin is written into the data register
in the write mode. The internal address counter is automatically incremented when
RWCK
falls.
Write Enable (
WE
)
Input pin for selecting the read mode, write mode or read modify write mode.
The read mode is set when
WE
is "H", and the write mode is set when
WE
is "L". When
WE
falls from
"H" to "L" while
RWCK
is active, the read modify write mode is set.
Data Input (D
IN
)
Input pin for write data.
The information at the data input pin is stored at the falling edge of
RWCK
in the write mode, and
at the falling edge of
WE
in the read modify write mode.
Data Output (D
OUT
)
The data output pin is always kept in the high impedance state when
RWCK
or
CS
is kept at "H".
When "H" or "L" information is read in the read operation, the output pin is set to "H" to "L" and holds
the read information until
RWCK
is again set to "H". In the early write mode the output pin maintains
the high impedance state, so I/O common operation by connecting D
IN
and D
OUT
is possible.
Self/Auto Refresh Select (
RS/A
)
Pin for selecting a refresh mode in order to retain memory cell data.
If the
RS/A
pin is set to "L" level, the self-refresh mode is selected and no external refresh control is
required. If the
RS/A
pin is set to "H" level, the auto-refresh mode is selected and refresh operation
is required to retain memory cell data.
Refresh Clock Input (
RFSH
)
Input pin for controlling the external refresh when the auto refresh mode is selected. When the auto-
refresh mode is selected, 1024 refresh operations are required within 100ms via the
RFSH
pin while
the
RWCK
is at "H" level.
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