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參數(shù)資料
| 型號： | MSM6242BGS-K |
| 廠商： | LAPIS SEMICONDUCTOR CO LTD |
| 元件分類： | 時鐘/數(shù)據(jù)恢復(fù)及定時提取 |
| 英文描述： | 0 TIMER(S), REAL TIME CLOCK, PDSO24 |
| 封裝： | 0.430 INCH, 1.27 MM PITCH, PLASTIC, SOP-24 |
| 文件頁數(shù)： | 13/24頁 |
| 文件大?。?/td> | 293K |
| 代理商： | MSM6242BGS-K |
OKI Semiconductor
MSM6242B
19/23
FEDL6242B-02
SUPPLEMENTARY DESCRIPTION
When "0" is written to the IRQ FLAG bit, the IRQ FLAG bit is cleared. However, if "0" is
assigned to the IRQ FLAG bit when written to the other bits, the 30-sec ADJ bit and the
HOLD bit, the IRQ FLAG = 1 and was generated before the writing and IRQ FLG = 1
generated in a moment then will be cleared. To avoid this, always set "1" to the IRQ
FLAG unless "0" is written to it intentionally. By writing "1" to it, the IRQ FLAG bit
does not become "1".
Since the IRQ FLAG bit becomes "1" in some cases when rewriting either of the t
1, t0, or
ITRPT/STND bit of register C
E, be sure to write "0" to the IRQ FLAG bit after writing to
make valid the IRQ FLAG = 1 to be generated after it.
*
The relationship between SDT.P OUT and IRQ FLAG bit is shown below:
STD.P OUT
IRQ FLAG bit
open
"L"
1
0
approx. 1.95 ms
TYPICAL APPLICATION — POWER SUPPLY CIRCUIT
Figure 20
100
10 k
VDD
MSM
6242B
VSS
4.7
F
C
M
RL
1.5
2 = 3 V
DRY CELLS
+5 V
RL
VDD
MSM
6242B
VSS
4.7
F
22
F
100
51 k
10 k
+5 V
Figure 19
RIPPLE
OPERATING: 20 mV P-P
BATTERY BACKUP: 0 mV
VDD
MSM
6242B
VSS
100
4.7
F
220
+5 V
~ 6.5 V
~
D1
RL
1.2
3 = 3.6 V
Ni – Cd
1.2
3 = 3.6 V
Ni – Cd
Figure 21
4.7
F: tantalum
VCE (SAT.) = 0.1 V
B
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MSM6242BGS-KR1 | 制造商:ROHM Semiconductor 功能描述: |
| MSM6242BRS | 制造商:ROHM Semiconductor 功能描述: 制造商:OK International 功能描述: |
| MSM6242BRS-7 | 制造商:ROHM Semiconductor 功能描述:Directly connected to the bus real-time clock |
| MSM6250 | 制造商:QUALCOMM 制造商全稱:QUALCOMM 功能描述:CHIPSET SOLUTION |
| MSM6252 | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:64words X Bit FIFO |
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