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參數(shù)資料
| 型號(hào)： | MSM6242BGS-K |
| 廠商： | LAPIS SEMICONDUCTOR CO LTD |
| 元件分類： | 時(shí)鐘/數(shù)據(jù)恢復(fù)及定時(shí)提取 |
| 英文描述： | 0 TIMER(S), REAL TIME CLOCK, PDSO24 |
| 封裝： | 0.430 INCH, 1.27 MM PITCH, PLASTIC, SOP-24 |
| 文件頁數(shù)： | 11/24頁 |
| 文件大?。?/td> | 293K |
| 代理商： | MSM6242BGS-K |
OKI Semiconductor
MSM6242B
18/23
FEDL6242B-02
3. CH
1 (Chip Select)
V
IH and VIL of CH1 has 3 functions.
a)
To accomplish the interface with a microcontroller/microprocessor.
b)
To inhibit the control bus, data bus and address bus and to reduce input gate pass
current in the stand-by mode.
c)
To protect internal data when the mode is moved to and from standby mode.
To realize the above functions:
a)
More than 4/5 V
DD shoud be applied to the MSM6242B for the interface with a
microcontroller/microprocessor in 5 V operation.
b)
In moving to the standby mode, 1/5 V
DD should be applied so that all data buses should
be disabled. In the standby mode, approx. 0 V should be applied.
c)
To and from the standby mode, obey following Timing chart.
To Standby Mode
VDD
CS1
From Standby Mode
4 to 6 V
2 to 4 V
4 V
2
s (MIN)
VDD
2
5
2
s (MIN)
VDD
1
5
VDD
4
5
CS0 : H
or WR : H
YES
NO
4. Set SDT.P at Alarm Mode
Set alarm at 9:00
Read Register CD
D2 = 1?
AM 9:00?
Read H10 and
H10 Cotent
MASK BIT ← 0
ITRPT/STND BIT ← 1
t1, t0 ← 1
Start interruption
CPU Activation
CPU HALT
or
CPU STAND BY
Repeat
YES
NO
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PDF描述 |
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| MSM6242BRS | 0 TIMER(S), REAL TIME CLOCK, PDIP18 |
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| MSM63182-XXXGS-K | 4-BIT, MROM, 2 MHz, MICROCONTROLLER, PQFP128 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MSM6242BGS-KR1 | 制造商:ROHM Semiconductor 功能描述: |
| MSM6242BRS | 制造商:ROHM Semiconductor 功能描述: 制造商:OK International 功能描述: |
| MSM6242BRS-7 | 制造商:ROHM Semiconductor 功能描述:Directly connected to the bus real-time clock |
| MSM6250 | 制造商:QUALCOMM 制造商全稱:QUALCOMM 功能描述:CHIPSET SOLUTION |
| MSM6252 | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:64words X Bit FIFO |
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