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參數(shù)資料
| 型號： | MSM54C865-80 |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | 65,536-Word X 8-Bit Multiport DRAM |
| 中文描述： | 65,536字× 8位多端口內(nèi)存 |
| 文件頁數(shù)： | 33/44頁 |
| 文件大?。?/td> | 479K |
| 代理商： | MSM54C865-80 |
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MSM54C865
Semiconductor
33/44
PIN FUNCTION
Address Input : A0 - A7
The 16 address bits decode an 8-bit location of the 525,288 locations in the MSM54C865-JS/ZS
memory array. The address bits are multiplexed to 8 address input pins (A0 to A7) as standard
DRAM. 8 row address bits are latched at the falling edge of
RAS
. The following 8 column address
bits are latched at the falling edge of
CAS
.
Row Address Strobe :
RAS
RAS
is a basic RAM control signal. The RAM port is in standby mode when the
RAS
level is
"high". As the standard DRAM's
RAS
signal function,
RAS
is control input that latches the row
address bits and random access cycle begins at the falling edge of
RAS
.
In addition to the conventional
RAS
signal function, the level of the input signals,
CAS
,
DT
/
OE
,
WB
/
WE
, DSF, and
SE
, at the falling edge of
RAS
, determines the MSM54C865-JS/ZS
operation modes.
Column Address Strobe :
CAS
As the standard DRAM's
CAS
signal function,
CAS
is the control signal that latches the column
address input and the states of the special function input DSF to select, in conjunction with the
RAS
control, either read/write operations or the special block write feature on the RAM port
when the DSF is held "low" at the falling edge of
RAS
.
CAS
also acts as a RAM port output enable
signal.
Data Transfer/Out Enable :
DT
/
OE
DT
/
OE
is also a control input signal having multiple functions. As the standard DRAM's
OE
signal function,
DT
/
OE
is used as an output enable control when
DT
/
OE
is "high" at the falling
edge of
RAS
.
In addition to the conventional
OE
signal function, a data transfer operation is started between
the RAM port and the SAM port when
DT
/
OE
is "low" at the falling edge of
RAS
.
Write per Bit/ Write Enable :
WB
/
WE
WB
/
WE
is also a control input signal having multiple functions. As the standard DRAM's
WE
signal function, it is used to write data into the memory on the RAM port when
WB
/
WE
is "high"
at the falling edge of
RAS
.
In addition to the conventional
WE
signal function, the
WB
/
WE
determines the write-per-bit
function when
WB
/
WE
is "low" at the falling edge of
RAS
, during RAM port operations. The
WB
/
WE
is "high" at the falling edge of
RAS
, the data is transferred from RAM to SAM (read
transfer). When
WB
/
WE
is "low" at the falling edge of
RAS
, the data is transferred SAM to RAM
(write transfer).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MSM54C865-80JS | 65,536-Word X 8-Bit Multiport DRAM |
| MSM54C865-80ZS | 65,536-Word X 8-Bit Multiport DRAM |
| MSM54V12222A | 262,214 Words x 12 Bits FIELD MEMORY |
| MSM54V12222B | 262,214-Word 】 12-Bit Field Memory |
| MSM54V12222B-20JS | 262,214-Word 】 12-Bit Field Memory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MSM54V12222A-30TS-K | 制造商:OKI Semiconductor 功能描述:FIELD/FRAME/LINE MEMORY, 44 Pin, Plastic, TSOP |
| MSM54V12222B-25JDR17 | 制造商:ROHM Semiconductor 功能描述: |
| MSM54V12222B-25JSDR1 | 制造商:ROHM Semiconductor 功能描述: |
| MSM54V12222B-25T3-K7 | 制造商:ROHM Semiconductor 功能描述: |
| MSM54V12222B-25T3R17 | 制造商:ROHM Semiconductor 功能描述: |
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