參數(shù)資料
型號: MSM54C865-70
廠商: OKI SEMICONDUCTOR CO., LTD.
英文描述: 65,536-Word X 8-Bit Multiport DRAM
中文描述: 65,536字× 8位多端口內(nèi)存
文件頁數(shù): 39/44頁
文件大?。?/td> 479K
代理商: MSM54C865-70
MSM54C865
Semiconductor
39/44
DATA TRANSFER OPERATION
The MSM54C865 features two types of bidirectional data transfer capability between RAM and
SAM, as shown in Figure 1 below.
1) Conventional (non split) transfer : 256 words by 8 bits of data can be loaded from RAM to SAM
(Read transfer) or from SAM to RAM (write transfer).
2) Split transfer : 128 words by 8 bits of data can be loaded from the lower/upper half of the RAM
to the lower/upper half of the SAM (Split read transfer) or from the lower/upper half of SAM
to the lower/upper half of RAM (Split write transfer).
The conventional transfer and split transfer modes are controlled by the DSF input signal.
256
256
8
Memory
Array
256
8
256
128
8
Memory
Array
128
8
256
128
8
Memory
Array
128
8
1) Conventional Transfer
2) Split Transfer
Figure 1.
The MSM54C865 supports five types of transfer operation : Read transfer, Split read transfer,
Write transfer, Pseudo write transfer and Split write transfer as shown in truth table. Data
transfer is invoked by holding the
DT
/
OE
signal "low" at the falling edge of
RAS
. The type of
transfer operation is determined by the state of
CAS
,
WB
/
WE
,
SE
and DSF latched at the falling
edge of
RAS
. During conventional transfer operations, the SAM port is switched from input to
output mode (Read transfer) or output to input mode (Write/Pseudo write transfer) whereas it
remains unchanged during split transfer operation (Split read transfer or Split write transfer).
相關(guān)PDF資料
PDF描述
MSM54C865-70JS 65,536-Word X 8-Bit Multiport DRAM
MSM54C865-70ZS 65,536-Word X 8-Bit Multiport DRAM
MSM54C865-80 65,536-Word X 8-Bit Multiport DRAM
MSM54C865-80JS 65,536-Word X 8-Bit Multiport DRAM
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