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參數(shù)資料
| 型號： | MSM54C865-70 |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | 65,536-Word X 8-Bit Multiport DRAM |
| 中文描述： | 65,536字× 8位多端口內(nèi)存 |
| 文件頁數(shù)： | 38/44頁 |
| 文件大?。?/td> | 479K |
| 代理商： | MSM54C865-70 |
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MSM54C865
Semiconductor
38/44
SAM PORT OPERATION
Single Register Mode
High speed serial read or write operation can be performed through the SAM port independent
of the RAM port operation, except during read/write transfer cycles.
The preceding transfer operation determines the direction of data flow through the SAM port.
If the preceding transfer is a read transfer, the SAM port is in the output made. If the preceding
transfer is write or pseudo write transfer, the SAM port is in the input mode.
The pseudo write transfer only switches the SAM port from output mode to input mode (Data
is not transffered from SAM port to RAM port).
Serial data can be read out of the SAM after a read transfer has been performed. The data is
shifted out of the SAM starting at any of the 256 bits locations.
The TAP location corresponds to the column address selected at the falling edge of
CAS
during
the read or write transfer cycle. The SAM register is configured as a circular data register. The
data is shifted out sequentially starting from the selected TAP location to the most significant bit
(255) and then wraps around the least significant bit (0).
Split Register Mode
In split register mode, data can be shifted into or out of one half of the SAM while a split read
or split write transfer is being performed on the other half of the SAM.
Conventional (non split) read, write, or pseudo write transfer cycle must precede any split read
or split write transfers. The split read and write transfers will not change the SAM port mode set
by preceding conventional transfer operation. In the split register mode, serial data can be shifted
in or out of one of the split SAM registers starting from any at the 128 TAP locations, excluding
the last address of each split SAM. Data is shifted in or out sequentially starting from the selected
TAP location to the most significant bit (127 or 255) of the first split SAM. Then the SAM pointer
moves to the TAP location selected for the second split SAM to shift data in or out sequentially
starting from this TAP location to the most significant bit (255 or 127) and finally wraps around
to the least significant bit.
0 1 2
127
128
255
TAP
TAP
129
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MSM54C865-70JS | 65,536-Word X 8-Bit Multiport DRAM |
| MSM54C865-70ZS | 65,536-Word X 8-Bit Multiport DRAM |
| MSM54C865-80 | 65,536-Word X 8-Bit Multiport DRAM |
| MSM54C865-80JS | 65,536-Word X 8-Bit Multiport DRAM |
| MSM54C865-80ZS | 65,536-Word X 8-Bit Multiport DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MSM54V12222A-30TS-K | 制造商:OKI Semiconductor 功能描述:FIELD/FRAME/LINE MEMORY, 44 Pin, Plastic, TSOP |
| MSM54V12222B-25JDR17 | 制造商:ROHM Semiconductor 功能描述: |
| MSM54V12222B-25JSDR1 | 制造商:ROHM Semiconductor 功能描述: |
| MSM54V12222B-25T3-K7 | 制造商:ROHM Semiconductor 功能描述: |
| MSM54V12222B-25T3R17 | 制造商:ROHM Semiconductor 功能描述: |
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