參數(shù)資料
型號： MSM54C865-10
廠商： OKI SEMICONDUCTOR CO., LTD.
英文描述： 65,536-Word X 8-Bit Multiport DRAM
中文描述： 65,536字× 8位多端口內(nèi)存
文件頁數(shù)： 40/44頁
文件大小： 479K
代理商： MSM54C865-10
MSM54C865
Semiconductor
40/44
Read Transfer Operation
Read transfer consists of loading a selected row of data from the RAM into the SAM register.
A read transfer is invoked by holding
CAS
"high" ,
DT
/
OE
"low",
WB
/
WE
"high", and DSF "low"
at the falling edge of
RAS
. The low address selected at the falling edge of
RAS
determines the
RAM row to be transferred into the SAM. The transfer cycle is completed at the rising edge of
DT
/
OE
. When the transfer is completed, the SAM port is set into the output mode. In a read/real time
read transfer cycle, the transfer of a new row of data is completed at the rising edge of
DT
/
OE
and this data becomes valid on the SIO lines after the specified access time t
SCA
from the rising
edge of the subsequent SC cycles. The start address of the serial pointer of the SAM is determined
by the column address selected at the falling edge of
CAS
. In a read transfer cycle (which is
preceded by a write transfer cycle), SC clock must be held at a constant V
IL
or V
IH
, after the SC
high time has been satisfied. A rising edge of the SC clock must not occur until after the specified
delay t
TSD
from the rising edge of
DT
/
OE
.
In a real time transfer cycle ( which is preceded by another read transfer cycle), the previous
row data appears on the SIO lines until the
DT
/
OE
signal goes "high" and the serial access time
t
SCA
for the following serial clock is satisfied. This feature allows for the first bit of the new row
of data to appear on the serial output as soon as the last bit of the previous row has been strobed
without any timing loss. To make this continuous data flow possible, the rising edge of
DT
/
OE
must be synchronized with
RAS
,
CAS
and the subsequent rising edge of SC (t
RTH
, t
CTH
, and t
TSL
/
t
TSD
must be satisfied).
Write Transfer Operation
Write transfer cycle consists of loading the content of the SAM register into a selected row of
the RAM. If the SAM data to be transferred must first be loaded through the SAM, a pseudo write
transfer operation must precede the write transfer cycles. A write transfer is invoked by holding
CAS
"high",
DT
/
OE
"low",
WB
/
WE
"low",
SE
"low" and DSF "low" at the falling edge of
RAS
. This
write transfer is selectively controlled per RAM I/O block by setting the mask data on the Wi/
Oi lines at the falling edge of
RAS
. The row address selected at the falling edge of
RAS
determines
the RAM row address into which the data will be transferred. The column address selected at the
falling edge of
CAS
determines the start address of the serial pointer of the SAM. After the write
transfer is completed, the SIO lines are set in the input mode so that serial data synchronized with
the SC clock can be loaded. When consecutive write transfer operations are performed, new data
must not be written into the serial register until the
RAS
cycle of the preceding write transfer is
completed. Consequently, the SC clock must be held at a constant V
IL
or V
IH
during the
RAS
cycle. A rising edge of the SC clock is only allowed after the specified delay t
SRD
from the rising
edge of
RAS
, at which time a new row of data can be written in the serial register.
Pseudo Write Transfer Operation
Pseudo write transfer cycle must be performed before loading data into the serial register after
a read transfer operation has been executed. The only purpose of a pseudo write transfer is to
change SAM port mode from output mode to input mode (A data transfer from SAM to RAM
does not occur). After the serial register is loaded with new data, a write transfer is invoked by
holding
CAS
"high",
DT
/
OE
"low",
WB
/
WE
"low",
SE
"high" and DSF "low" at the falling edge
of
RAS
. The timing conditions are the same as the one for the write transfer cycle except for the
state of
SE
at the falling edge of
RAS
.
相關(guān)PDF資料
PDF描述
MSM54C865-10JS 65,536-Word X 8-Bit Multiport DRAM
MSM54C865-10ZS 65,536-Word X 8-Bit Multiport DRAM
MSM54C865-70 65,536-Word X 8-Bit Multiport DRAM
MSM54C865-70JS 65,536-Word X 8-Bit Multiport DRAM
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