- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄378013 > MSM54C865-10 (OKI SEMICONDUCTOR CO., LTD.) 65,536-Word X 8-Bit Multiport DRAM PDF資料下載
參數(shù)資料
| 型號： | MSM54C865-10 |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | 65,536-Word X 8-Bit Multiport DRAM |
| 中文描述： | 65,536字× 8位多端口內(nèi)存 |
| 文件頁數(shù)： | 34/44頁 |
| 文件大?。?/td> | 479K |
| 代理商： | MSM54C865-10 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁當前第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁
MSM54C865
Semiconductor
34/44
Write Mask Data/Data Input and Output : W1/IO1 - W8/IO8
W1/IO1 - W8/IO8 have the functions of both Input/Output and a control input signal. As the
standard DRAM's I/O pins, input data on the W1/IO1 - W8/IO8 are written into the RAM port
during the write cycle. The input data is latched at the falling edge of either
CAS
or
WB
/
WE
,
whichever occurs later. The RAM data out buffers, which will output read data from
RAS
,
CAS
,
DT
/
OE
and column address are satisfied and the output data will remain valid as long as
CAS
and
DT
/
OE
are kept "low". The outputs will return to the high impedance state at the rising edge
of either
CAS
or
DT
/
OE
, whichever occurs earlier. In addition to the conventional I/O function,
the W1/IO1 - W8/IO8 have the function to set the mask data, which select mask input pins out
of eight input pins, W1/IO1 - W8/IO8, at the falling edge of
RAS
. Data is written to the DRAM
on data lines where the write-mask data is a logic "1". The write-mask data is valid for only one
cycle.
Serial Clock : SC
SC is a main serial cycle control input signal. All operation of SAM port are synchronized with
the serial clock SC. Data is shifted in or out of the SAM registers at the rising edge of SC. In a serial
read , the output data becomes valid on the SIO pins after the maximum specified serial access
time t
SCA
from the rising edge of SC.
The SC also increments the 8 bits serial pointer which is used to select the SAM address. The
pointer address is incremented in a wrap-around mode to select sequential locations after the
setting location which is determined by the column address in the read transfer cycle. When the
pointer reaches the most significant address location (decimal 255), the next SC clock will place
it at the least significant address location (decimal 0).
The SC must be held data constant V
IH
or V
IL
level during read/pseudo write/write-transfer
operations and should not be clocked while the SAM port is in the standby mode to prevent the
SAM pointer from being incremented.
Serial Enable :
SE
The
SE
is a serial access enable control and serial read/write control signal. In a serial read cycle,
SE
is used as an output control. In a serial write cycle,
SE
is used as a write enable control. When
SE
is "high", serial access is disable, however, the serial address pointer location is still
incremented when SC is clocked even when
SE
is "high".
Special Function Input : DSF
The DSF is latched at the falling edge of
RAS
and
CAS
and allows for the selection of several
RAM port and transfer operating modes. In addition to the conventional multiport DRAM, the
special function consisting of flash write, block write, load/read color register and split read/
write transfer can be invoked.
Special Function Output : QSF
QSF is an output signal which, during split register mode, indicates which half of the split SAM
is being accessed. QSF "low" indicates that the lower split SAM (0-127) is being accessed. QSF
'high" indicates that the upper SAM (128-255) is being accessed.
QSF is monitored so that after it toggles and after allowing for a delay of t
STS
, split read/write
transfer operation can be performed on the non-active SAM.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MSM54C865-10JS | 65,536-Word X 8-Bit Multiport DRAM |
| MSM54C865-10ZS | 65,536-Word X 8-Bit Multiport DRAM |
| MSM54C865-70 | 65,536-Word X 8-Bit Multiport DRAM |
| MSM54C865-70JS | 65,536-Word X 8-Bit Multiport DRAM |
| MSM54C865-70ZS | 65,536-Word X 8-Bit Multiport DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MSM54V12222A-30TS-K | 制造商:OKI Semiconductor 功能描述:FIELD/FRAME/LINE MEMORY, 44 Pin, Plastic, TSOP |
| MSM54V12222B-25JDR17 | 制造商:ROHM Semiconductor 功能描述: |
| MSM54V12222B-25JSDR1 | 制造商:ROHM Semiconductor 功能描述: |
| MSM54V12222B-25T3-K7 | 制造商:ROHM Semiconductor 功能描述: |
| MSM54V12222B-25T3R17 | 制造商:ROHM Semiconductor 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復。